First of all, please don't do things like loading "41215" into QMR. I shouldn't have to pick up a hex calculator to convert that back into bits to see how you're programming the chip. It is almost as if you are trying to make your code as hard to read as possible. You don't need to use raw hex either (like you do elsewhere) as the register bit meanings should already be defined in one of your system header files. Your code will be a lot easier for you and everyone else to read if you write it this way.
Here's an example of poor code in our system and how it should have been written:
uint16_t qmr = 0x8004 | ((is_words?0:8)<<10); // 10000010 00000100 - 10MHz uint16_t qwr = 0x1000 | ((p->num-1)<<8); // 0001 nnnn 0000 0000 uint16_t qdlr = 0x8001; // go with QCD=0 and DTL=1 if ( p->options & QSPI_DELAY ) { /* Doesn't set DTL=14, but sets to 15 unintentionally... */ qdlr |= 0x0e; // hack which is the right t_conv for ADC } MCF_QSPI_QMR = qmr; MCF_QSPI_QWR = qwr; MCF_QSPI_QDLYR = qdlr;=================== The first bit should have been written like ======== uint16_t qmr = MCF_QSPI_QMR_MSTR | MCF_QSPI_QMR_BAUD(4) | MCF_QSPI_QMR_BITS(is_words?0:8); uint16_t qwr = MCF_QSPI_QWR_CSIV | MCF_QSPI_QWR_ENDQP(p->num - 1); uint16_t qdlr = MCF_QSPI_QDLYR_SPE | MCF_QSPI_QDLYR_QCD(0) | MCF_QSPI_QDLYR_DTL(1); if ( p->options & QSPI_DELAY ) { qdlr = MCF_QSPI_QDLYR_SPE | MCF_QSPI_QDLYR_QCD(0) | MCF_QSPI_QDLYR_DTL(QSPI_DTL_ADC); }Please use the "[C]" button on this forum to insert code like I did for the above section. It makes it easier to read.
Search this forum for "QSPI" and read through all the previous problems. Read through this one:
https://community.freescale.com/message/50239#50239
You should follow the links to Rich T's QSPI drivers and use them instead of trying to write your own.
Specifically the remarks that hint at the cause of your problem: "If DT = 1, you can shrink or grow the delay by changing the value of QDLYR[DTL]. If DT = 0, a standard delay period is used. Time is needed to ensure the transfer RAM is loaded."
If you're finding that you need this delay, you should not add it with a "for loop". That is dangerous for a whole lot of reasons. The QSPI has programmable delays after transfers. Read up on how to set these. If you need a longer delay then set "DT" and "QDLYR[DTL]."
In my manual (MCF5329, but same QSPI pretty much), the "Transfer Delays" section says:
Adequate delay between transfers must be specified for long data streams becausethe QSPI module requires time to load a transmit RAM entry for transfer. Receivingdevices need at least the standard delay between successive transfers. If theinternal bus clock is operating at a slower rate, the delay between transfersmust be increased proportionately.
I don't know what they mean by the last sentence either, but it must mean something...
The "delay" might not be your problem though. There are two obvious bugs in your code I've just noticed:
while(!MCF5272_RD_QSPI_QIR){} //Wait untill SPIF is set to 1MCF5272_WR_QSPI_QIR(0x00); //Reset SPIF
The first line isn't waiting until SPIF is one - it is waiting for ANY bit to be set in this register. So if you're getting error bits set you won't see them. You should explicitly test the bit you're waiting for for when you do get an error. And test for error bits and print diagnostics if they get set. That will save you some time.
The second line won't "Reset SPIF". It won't do anything at all. Read the manual and read what "W1C" means. The SPIF bit description states "Writing a 1 to this bit (w1c) clears it and writing 0 has no effect."
So you're never clearing SPIF and since that's the bit you're waiting on it should explain your problem.
Tom