MCF52259/MCF52256 FB_CLK pin

[JMAC]

Hello everyone.

I am wiring up an external dual-port RAM to the mini-FlexBus on the MCF52256, but I'm havuing trouble figuring out where the FB_CLK woul be on the 144 pin LQFP package.  Although its described in the text of the Flexbus secton, its not shown anywhere on the pin assigment.  Can anyone shed some light on this?  Its mentioned in the text, but then not shown in the pin tables.  I don't even see the CLKOUT pin.  I had the same trouble sorting out some of the BDM/JTAG pins, so I figure this output clock pin is a dual-labled pin not shown completetly?.....

Thanks much.

[cutworth]

Hi,

There is a register in Table 15-1(Reference manual) named CLKOUTPAR at address 0x100074, this is used to select the output value of FB_CLK since it could be Fsys or Fsys/2. Unfortunate, it is not stated in the reference manual how to use it. Here is the code sample for how to use this register:

#define MCF_GPIO_CLKOUTPAR  (*(vuint8 *)(0x40100077))

      MCF_GPIO_CLKOUTPAR = 0x0;   // off

      MCF_GPIO_CLKOUTPAR = 0x1;   // clkout (80Mhz)

      MCF_GPIO_CLKOUTPAR = 0x2;   // off

      MCF_GPIO_CLKOUTPAR = 0x3;   // fb_clk  (40Mhz if MiniFlexBus default 1:2 Mode)

Hope this can help.

[mjbcswitzerland]

Hi

Many thanks, that was the missing info. that was required.

Regards

Mark

[Miggi]

Hi,

so when CLKOUTPAR = 0x3 and CCE[MBMOD] = 0x1 (1:1 Mode)

Pin M3(144 MAPBGA) should be FB_CLK @ SYSCLK.

And when CLKOUTPAR = 0x3 and CCE[MBMOD] = 0x0 (1:2 Mode)

Pin M3(144 MAPBGA) should be FB_CLK @ SYSCLK/2.

Is this assumption correct?

For me the first assuption (1:1 Mode ) it is not possible to realize as shown above.

It seems that Pin M3(144 MAPBGA) is SYSCLK if CLKOUTPAR = 0x1 and SYSCLK/2 if CLKOUTPAR = 0x3, regardless CCE[MBMOD] setting.

How can I assign FB_CLK to Pin M3(144 MAPBGA) if FB_CLK is in 1:1 Mode?

Michael

[cutworth]

Hi,

You can configure M3 to use as FB_CLK and connect it to external synchronous device like the dual-port FIFO ram. 

[mjbcswitzerland]

Hi

Any tips on how to actually do this?

That is, in which register can it be programmed?

The FB_CLK is a tertiary function on the TCLK/PSTCLK line (pin M3 on the 144 pin MAPBGA package) but the pin doesn't seem to belong to any port which can be controlled via a (PORT)PAR register. Therefore I assume that this is controlled from another block (like the System Control Module, or the the MiniFlex module itself) but the method hasn't been discovered yet...

Regards

Mark

[cutworth]

Something to add,

Pin M3/43:
    TCLK/PSTCLK
    Secondary function: CLKOUT
    Tertiary function: FB_CLK

So when you are not using BDM, you can configure this pin to output FB_CLK, so you can watch the FB_CLK with oscilloscope.

[mjbcswitzerland]

Hi

Could you inform how the pin can be configured to connect the FB_CLK?

Many thanks

Mark

[cutworth]

Hi,

The FB_CLK signal is just internal synchronization signal which determines how fast the external access could be. On MCF52259 it could be set to equal fsys or Fsys/2 and you can refer to bus cycle execution and timing examples in the reference manual to get a clear point of the usage of FB_CLK. 

The Minibus can connect asynchrous devices like SRAM, so there is no specific need for an clock signal like that on a SDRAM.

[mjbcswitzerland]

Hi

Pin M3/43:
    TCLK/PSTCLK
    Secondary function: CLKOUT
    Tertiary function: FB_CLK

I don’t actually see how this is controlled, but I expect that it is automatically activated when the debugger is not enabled and when the flex bus is active.

Regards

Mark



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[MrBean]

Current MCF52259 Ref Manual signal description table is crap.

The MCF52259_GPIO.h and other header files in the downloadable EVB source is the most clarifying documentation on it.