MCF5223x Flash programming - confusing

[MrBean]

The documentation of the coldfire flash module is very confusing.
It speaks of logical/physical blocks, pages and sectors.
It speaks of a number of different clocks.
There is little explanation as to what is what.

Interresting reading:
http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=3830
http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=4262&query.id=96555#M...

For the clocks part i've worked out this:

Code:

void mcf52235_init_flash(void){ // Set CFMCLKD to get a flashCLK between 150 kHz and 200 kHz. // Array damage due to overstress can occur when fCLK is less than 150 kHz.  // Incomplete programming and erasure can occur when fCLK is greater than 200 kHz. // Not so clear in the RefManual, but it works out to be : //  flashCLK = FSYS/2 /(8*MCF_CFM_CFMCLKD_PRDIV8) /(MCF_CFM_CFMCLKD_DIV+1)  // Calculate the divider to get a flashCLK closest to 200kHz (smaller or equal) : if (FSYS > 25600000) {  MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8|MCF_CFM_CFMCLKD_DIV((FSYS/2/8/200000)-1); } else {  MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_DIV((FSYS/2/200000)-1); } //MCF_CFM_CFMPROT=0;//No sector is protected //MCF_CFM_CFMSACC=0;//Flash sectors are placed in supervisor address space //MCF_CFM_CFMDACC=0; //MCF_CFM_CFMMCR=0x20; MCF_CFM_CFMMCR = 0; —–}

 

I still have one question :

Since flashCLK seems to be based on the flash bus clock:
Is the FSYS/2 part caused by and thus influenced by the CFMCLKSEL[CLKSEL] bits ?

[RichTestardi]

> I still have one question :

> Since flashCLK seems to be based on the flash bus clock:
> Is the FSYS/2 part caused by and thus influenced by the CFMCLKSEL[CLKSEL] bits ?

I believe the short answer is "no".

The docs for the MCF52223 and MCF52235 are a bit inconsistent in their usage of the term Fsys, if I remember.

In the MCF52223 Reference Manual there is a *great* picture in section 5.5 that shows Fsys as being the CPU clock, and it is divided by 2 to get the bus clock for all peripherals except BDM and potentially USB.  This picture is unfortunately missing from the MCF52235 Reference Manual.

The "/2" is because of this divide by 2.

In my new code, I don't use the term Fsys at all any more, but instead use the CPU and bus frequencies explicitly -- maybe this makes it more clear:

Code:

   cpu_frequency = 60000000;    bus_frequency = cpu_frequency/2;    if (bus_frequency > 12800000) {        MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8|MCF_CFM_CFMCLKD_DIV((bus_frequency-1)/8/200000);    } else {        MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_DIV((bus_frequency-1)/200000);    }

 
The goal is to implement the algorithm in section 21.6 of the MCF52235 Reference Manual.

The flash controller module runs at the system clock frequency divided by 2, but

FCLK must be divided down from this frequency to a frequency between 150 kHz and 200 kHz. Use the

following procedure to set the PRDIV8 and DIV[5:0] bits in the clock configuration register.

-- Rich

[MrBean]

Thanx !

Very usefull !! -> http://www.freescale.com/files/32bit/doc/ref_manual/MCF52223RM.pdf  : Figure 5-1. Clock Module Block Diagram

I believe there is an error in your MCF_CFM_CFMCLKD_DIV calculation.

Look at the position of the -1 in my calculation.

I believe that MCF_CFM_CFMCLKD_DIV = 0 means: divide by 1.

This is consistent with the max cpu clock that could be divided to 200kHz being 25600000 (the maximum divider being /64 ) before there is need to activate the predivider.

Message Edited by MrBean on 2008-11-27 04:42 PM

[RichTestardi]

> I believe there is an error in your MCF_CFM_CFMCLKD_DIV calculation.

> Look at the position of the -1 in my calculation.

Yes, I agree, thank you!!!  I've updated my code!

[RichTestardi]

Actually, now I'm not so sure...  The manual has a complex algorithm which I think is actually what I implemented faithfully (eliminating the need for the "if", by moving the "- 1" inside the divide):

CFMCLKD DIV bit field must be chosen such that the following equation is valid:

If PRDIV8 == 1 then FCLK = input clock / 8, else FCLK = input clock

If (FCLK[KHz] / 200KHz) is integer then DIV = (FCLK[KHz] / 200KHz) - 1,

else DIV = INT (FCLK[KHz] / 200kHz)

What do you think?

[MrBean]

I think you are right and that i did mis the fact that the define results in a non-rounded integer.

Didnt see that ...

This makes the integer clearer to me:

Code:

 // Calculate the divider to get a flashCLK closest to 200kHz (smaller or equal) : if (FSYS > 25600000) {  MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8|MCF_CFM_CFMCLKD_DIV((FSYS/2/8 -1)/200000); } else {  MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_DIV((FSYS/2 -1)/200000); }

 

[RichTestardi]

Yes, and my "/8" was in the wrong place still -- I believe where you ended is completely correct!!!

[MrBean]

  Ok. Thats solved then.

Now someone go update the Ref Manual

[J2MEJediMaster]

The missing figure has been noted from your conversations here and will be passed on to the appropriate docs people for correction.

---Tom