MC68000 chip select

[prasadht]

Hi All,

Greetings!!!

Currently I am working on MC68360 processor to enable the chip select 7. I am setting the Base register and Option register with the values 0x02010001 and 0xFFFFF004 respectively, But after turning on the board, I am not able to see the CS7 toggling.

Memory Map: 0x00000000 to 0xFFFFFFFF

SRAM Bank for CS7: 0x02010000 to 0x02011000

SRAM Bank for CS5: 0x02000000 to 0x02000800

Registers Address:

MBAR    EQU     $03FF00

PEPAR   EQU     $031016

GMR     EQU     $031040

BR7     EQU     $0310C0

OR7     EQU     $0310C4

MBAR code: 

moveq.l #7,d0 ; "0111" is the function code for CPU Space
movec d0,SFC ; Store "0111" into both the Src Fcn Code Reg
movec d0,DFC ; and the Dest. Fcn Code Reg
moves.l MBAR,d0 ; load MBAR value into d0
andi.l #$FFFFE000,d0 ; mask lower 13 bits
move.l d0,a5 ; save base address in a5

Port E assignment: MOVE.W    #$0094,PEPAR

Global Memory Register (GMR): MOVE.L    #$00001200,GMR

OR5 : MOVE.L    #$FFFF0004,OR5

BR5 : MOVE.L    #$02000001,BR5

OR7 : MOVE.L    #$FFFFF004,OR7

BR7 : MOVE.L    #$02010001,BR7

currently on CS7, no hardware connected.

We had configured registers for chip selects 0-6, thay all working. The CS7 we are trying to enable is not working. 

When we swapped BR5 and OR5 with BR7 and OR7, then CS7 working but CS5 is not working.

Please help me. Thank you.

[miduo]

Hello,

Please let me know what chip mask version you had. If you have a look at the chip errata, you will find below errata:

"An access to the memory range $3FF00 - $3FF0F immediately following an bus cycle which had FC3-0
= ‘0111’ will result in the chip select corresponding to that memory device not asserting for that specific
access. For example, if the stack pointer points to an address in the range $3FF00 - $3FF0F and an
interrupt occurs, the chip select corresponding to that memory device will not assert on the first access
of the stack frame push. Another situation would be an SDMA access to that memory immediately
following an interrupt acknowledge cycle. The workaround is to not place any memory in this
addressing range. This will be fixed in Rev. C.1."