Intermittent reset failures on 5282

[Hawkeye]

We are experiencing seemly random POR reset failures. There 3 different scenarios: 1) the board boots and runs properly; 2) board does not run and we see a finite (typically a burst of 4 pairs followed by a burst of 5 pairs) number of CS0* assertions; 3) board does not run and we see continuous toggling of CS0*. The scenarios occur in bunches. ie. it will work 5-6 times in a row then it will fail 5-6 times in a row. Our reset config pins specify an external, 16 bit boot and we have our boot loader stored in flash. All of the reset config pins seem correct, we just tried using a buffer for the ones shared with the data bus but it did not change the behaviour. Our actual board just uses pullups/pulldowns. We see the same two failing scenarios if our boot flash is erased. Can somebody please explain why (or point me to an explanation) we would see continuous toggling on CS0* with an erased boot flash? The clockout frequency is as expected. The time between RSTI de-assertion and RSTO de-assertion is as expected. Any suggestions on what I should look for next? Thanks

[RichTestardi]

Does reading the RSR on boot tell you anything?

We have a battery operated core that sometimes resets more than once on power-up, due to low voltage detect, until the rather slow/weak supply stabilizes.  We were unaware of this until we noticed the RSR bit often being set.  Now to attempt to mitigate this (and chase out the LVD early, before it might cause harm), we turn on all high-current peripherals (internal and external) immediately on boot.

See 29.4.2 Reset Status Register (RSR)

The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset condition is latched along with a value of 0 for the other reset sources that were not pending at the time of the reset condition. These values are then reflected in RSR. One or more status bits may be set at the same time.  The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset condition.

[Hawkeye]

Thanks for the suggestion Rich. Our problem ended up being due to another device on the that was holding TA* low when coming out of reset. While TA* was low the ColdFire was terminating its reads before the flash could drive its data on the bus. We did find that using 100 kohm pull downs on the reset config pins did not work but had not recognized that at the time of the original post due to the above failure. 10 kohm pulldowns work.