Instruction cache activation with DRAM for MCF54455

[mehrdad]

Hi,

I have a custom board which is similar to Freescale evaluation board for MCF54455. If I don't activate instruction cache on DRAM, everything running. However when I activate the instruction cache the code stops when start running from DRAM.

I used BDM to investigate. If the instruction is more than 32 bit, then the next data for instruction comes from different address and not the next 32 bits. Of course when instruction cache is not active everything is fine. I even removed DRAM address from ACR registers but still happening. By just activating cache this will happen.

Any help will be appreciated.

Regards,

Mehrdad

[McuG]

I know is an old post, were you able to find what the problem was ?

[mehrdad]

Hi McuG,

Yes. Address A0 and A1 was swapped in schematic by mistake. Without cache, no burst access to DRAM happened and everything was fine. Just the location to store values were different. However when burst mode used by activating cache, the values read from DRAM were wrong. Swapping the address lines on the board manually fixed the problem.

Cheers,

Mehrdad

[McuG]

Thank you for the update. Our problem seems to be timing related, but your reply pointed us to the right track - burst and DDR.

Regards