I’m trying to set up a prototype board with MCF5373 CPU a...

[Bastaix]

I’m trying to set up a prototype board with MCF5373 CPU and SDRAM (not DDR) and there I have some thing  miss configured.

The design is based on LOGIC MCF5373-10 CARD ENGINE replacing DDR by SDR 32 data bita.

The hardware have CPU pin “DRAMSEL to VPP” and  16 data bits flash memory attach to CPU D11..D31.

To do a hardware cheeking I took some initialisation functions code from evaluation project target doing  modifications to drive a different memories.

void sdramc_init (void)
{

 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_REF_EN; // elimina la preinicialitzacio del BDM

 /*
  * Check to see if the SDRAM has already been initialized
  * by a run control tool
  */
 if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF_EN))
 {

  /* SDRAM chip select initialization */
  
  /* Initialize SDRAM chip select */
        MCF_SDRAMC_SDCS0 = (0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
            | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_8MBYTE)
            );

        MCF_SDRAMC_SDCS1 = (0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS+SDRAM_SIZE)
            | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_8MBYTE)
            );
           

  /* Basic configuration and initialization   */

        MCF_SDRAMC_SDCFG1 = (vuint32)(0
   | MCF_SDRAMC_SDCFG1_SRD2RWP((int)(SDRAM_CASL + SDRAM_THZ + 2))
   | MCF_SDRAMC_SDCFG1_SWT2RDP(SDRAM_TWR)
   | MCF_SDRAMC_SDCFG1_RD_LAT((int)(SDRAM_CASL))
   | MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD))
   | MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP))
   | MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC))
   | MCF_SDRAMC_SDCFG1_WT_LAT(0)
            );
          
  MCF_SDRAMC_SDCFG2 = (vuint32)(0
   | MCF_SDRAMC_SDCFG2_BRD2RP(SDRAM_BL + 1)
   | MCF_SDRAMC_SDCFG2_BWT2RWP(SDRAM_BL + SDRAM_TWR - 2)
   | MCF_SDRAMC_SDCFG2_BRD2W((int)(SDRAM_CASL + SDRAM_BL + SDRAM_THZ))
   | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1)
            );
 
           
  /* Precharge and enable write to SDMR  */
        MCF_SDRAMC_SDCR = (0
   | MCF_SDRAMC_SDCR_MODE_EN
   | MCF_SDRAMC_SDCR_CKE
   | MCF_SDRAMC_SDCR_ADDR_MUX(0)
   | MCF_SDRAMC_SDCR_REF_CNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
   | MCF_SDRAMC_SDCR_PS_32
   | MCF_SDRAMC_SDCR_IPALL
            );           
           

  /* Write extended mode register  */
  MCF_SDRAMC_SDMR = (0
   | MCF_SDRAMC_SDMR_BNKAD_LEMR
   | MCF_SDRAMC_SDMR_AD(0x0)
   | MCF_SDRAMC_SDMR_CMD
            );
  
  /* Write mode register and reset DLL  */
  MCF_SDRAMC_SDMR = (0
   | MCF_SDRAMC_SDMR_BNKAD_LMR
   | MCF_SDRAMC_SDMR_AD(0x30 | (SDRAM_BL-1))
   | MCF_SDRAMC_SDMR_CMD
            );
    
  /* Execute a PALL command  */
  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
  
  /* Perform two REF cycles    */
  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
      
  /* Enable auto refresh and lock SDMR  */
  MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
        MCF_SDRAMC_SDCR |= (0
   | MCF_SDRAMC_SDCR_REF_EN
   | MCF_SDRAMC_SDCR_DQS_OE(0xC)
            );      
 }

}

and

void fbcs_init (void)
{

 MCF_GPIO_PAR_CS = 0x0000003E;
 
 MCF_FBCS5_CSMR = 0;
 MCF_FBCS4_CSMR = 0;
 MCF_FBCS4_CSMR = 0;

    /* FPGA chip select */
    MCF_FBCS2_CSAR = 0x10000000; //FPGA_ADDRESS;
    MCF_FBCS2_CSCR = (0
        | MCF_FBCS_CSCR_PS_16  
                    | MCF_FBCS_CSCR_AA   
                    | MCF_FBCS_CSCR_WS(3)  
                    | MCF_FBCS_CSCR_ASET(2)  
                    | MCF_FBCS_CSCR_RDAH(2)  
                    | MCF_FBCS_CSCR_WRAH(2));
 
   MCF_FBCS2_CSMR = (0
        |MCF_FBCS_CSMR_BAM_2M
                    | MCF_FBCS_CSMR_V);

    /* NANDFLASH chip select */
    MCF_FBCS1_CSAR = 0x10080000; //NANDFLASH_ADDRESS;
    MCF_FBCS1_CSCR = (0
        | MCF_FBCS_CSCR_PS_16  
                    | MCF_FBCS_CSCR_AA   
                    | MCF_FBCS_CSCR_WS(3)  
                    | MCF_FBCS_CSCR_ASET(2)  
                    | MCF_FBCS_CSCR_RDAH(2)  
                    | MCF_FBCS_CSCR_WRAH(2)); 

   MCF_FBCS1_CSMR = (0
        | MCF_FBCS_CSMR_BAM_2M
                    | MCF_FBCS_CSMR_V);                   

    /* Boot Flash connected to FBCS0 */
    MCF_FBCS0_CSAR = 0x00000000; //FLASH_ADDRESS;
    MCF_FBCS0_CSCR = (0
        | MCF_FBCS_CSCR_PS_16
        | MCF_FBCS_CSCR_BEM
                    | MCF_FBCS_CSCR_AA
                    | MCF_FBCS_CSCR_WS(0x3F));
                   
    MCF_FBCS0_CSMR = (0
        | MCF_FBCS_CSMR_BAM_32M
                    | MCF_FBCS_CSMR_V);
}

I’m send a local counter variable value to address from 0x40000000 to 0x4000FFFF in a endless loop and there appears a valid signals to SD_CS, SD_RAS, SD_CAS, SD_WE, and address  but the data bus do nothing the lower bits don’t change.

[Bastaix]

I fixed up the problem.

I attach a valit BDM file to configure a 32bits SDRAM and a 16bits FLASH.