20uA is what the Data Sheet says. I wouldn't expect there would be any way to lower it. hat's what you have to design for if you've selected this chip.
If you need a lower power draw then use an external SPI/I2C-connected RTC.
Search for "VSTBY" in this forum and you'll find a detailed post from March 2009 listing the power draw - up to 31.7uA in one test.
https://community.freescale.com/thread/51895
The usual reason why these chips draw more than the watch on your wrist is that they're made with different silicon processes, optimised for higher speed and power than your watch needs. The RTC and SRAM need to be read QUICKLY when the CPU is running. Sometimes there are unexpected "leakage paths" inside the chip as well that draw current. I've read Chip Errata detailing these problems. Sometimes they release new silicon to fix the problem, and other times it is "will never be fixed".
I'd also suggest measuring the current and then start grounding any floating pins on the CPU. It might be that a floating pin on a powered input gate is drawing some extra urrent.
Tom