How to generate M52235 UART interrupt?

[ylkoh]

Hi,

 Is there anybody can tell me how to generate UART0 interrupt?

 Currently, I can getchar/putchar from UART0 to Terminal already. But the problem is I am not able to generate an interrupt while Rx and Tx.

 Can somebody help me? it would be better to have an example.

 Thanks in advance.

Regards,

YL Koh

[Nouchi]

hi,

1 - Install your ISR routine in exeption table :   /* see Chap 15.6.3.1 to know  source number */
__VECTOR_RAM[64+13] = (uint32)YourISRFunction; 
2 -  Program interrupt controller                     /* see Chap 15.3.6  &  15.3.2*/
   MCF_INTC_ICR(13) |= MCF_INTC_ICR_IL(3) | MCF_INTC_ICR_IP(3);   /* set It level & priority */
   MCF_INTC_IMRL &= ~(MCF_INTC_IMRL_MASK13 + MCF_INTC_IMRL_MASKALL);  /* enable it */
3 - enable uart interrupt                               /* see chap 26.3.1 & 26.3.10 */
   MCF_UART_UMR(0) = what you need;         /*select interrupt Fifo full or RXRDY */
   MCF_UART_UIMR(0) = MCF_UART_UIMR_RXRDY_FU + MCF_UART_UIMR_TXRDY; /* enable interrupts */
4 - in your ISR routine, check status register   /* see chap 26.3.3 */
   ucStatus = MCF_UART_USR(0);            /* read status register */
   and deal with status register flags (error flags FE, OE and PE and RXTX flags TXRDY, FFULL or RXRDY)


Emmanuel

[ylkoh]

Hi BugMan,

 Thanks for you reply.

 BTW, I still can't get any interrupt.

 I am using vector table to generate the ISR

 vector4D: .long _uart0_handler

 Here is what I wrote.

void
mcf52235_uart_init(void)
{
 /*
 * Initialize all three UARTs for serial communications
 */

 register uint16 ubgs;

 /*
 * Set Port UA to initialize URXD0/UTXD0
 */
   MCF_GPIO_PUAPAR = 0
       | MCF_GPIO_PUAPAR_RXD0_RXD0
       | MCF_GPIO_PUAPAR_TXD0_TXD0;

   MCF_GPIO_PUBPAR = 0
       | MCF_GPIO_PUBPAR_RXD1_RXD1
       | MCF_GPIO_PUBPAR_TXD1_TXD1;

   MCF_GPIO_PUCPAR = 0
       | MCF_GPIO_PUCPAR_RXD2_RXD2
       | MCF_GPIO_PUCPAR_TXD2_TXD2;

 /*
 * Reset Transmitter
 */
 MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;
 MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;
 MCF_UART2_UCR = MCF_UART_UCR_RESET_TX;

 /*
 * Reset Receiver
 */
 MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;
 MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;
 MCF_UART2_UCR = MCF_UART_UCR_RESET_RX;

 /*
 * Reset Mode Register
 */
 MCF_UART0_UCR = MCF_UART_UCR_RESET_MR;
 MCF_UART1_UCR = MCF_UART_UCR_RESET_MR;
 MCF_UART2_UCR = MCF_UART_UCR_RESET_MR;

 /*
 * No parity, 8-bits per character
 */
 MCF_UART0_UMR = (0
  | MCF_UART_UMR_RXIRQ
  | MCF_UART_UMR_RXRTS
  | MCF_UART_UMR_PM_NONE
  | MCF_UART_UMR_BC_8 );
 MCF_UART1_UMR = (0
  | MCF_UART_UMR_RXIRQ
  | MCF_UART_UMR_RXRTS
  | MCF_UART_UMR_PM_NONE
  | MCF_UART_UMR_BC_8 );
 MCF_UART2_UMR = (0
  | MCF_UART_UMR_PM_NONE
  | MCF_UART_UMR_BC_8 );

 /*
 * No echo or loopback, 1 stop bit
 */
 MCF_UART0_UMR = (0
  | MCF_UART_UMR_CM_NORMAL
  | MCF_UART_UMR_SB_STOP_BITS_1);
 MCF_UART1_UMR = (0
  | MCF_UART_UMR_CM_NORMAL
  | MCF_UART_UMR_SB_STOP_BITS_1);
 MCF_UART2_UMR = (0
  | MCF_UART_UMR_CM_NORMAL
  | MCF_UART_UMR_SB_STOP_BITS_1);

 /*
 * Set Rx and Tx baud by SYSTEM CLOCK
 */
 MCF_UART0_UCSR = (0
  | MCF_UART_UCSR_RCS_SYS_CLK
  | MCF_UART_UCSR_TCS_SYS_CLK);
 MCF_UART1_UCSR = (0
  | MCF_UART_UCSR_RCS_SYS_CLK
  | MCF_UART_UCSR_TCS_SYS_CLK);
 MCF_UART2_UCSR = (0
  | MCF_UART_UCSR_RCS_SYS_CLK
  | MCF_UART_UCSR_TCS_SYS_CLK);

 /*
 * Mask all UART interrupts
 */
 uart0_interrupt_init(); // added by ylkoh
 uart1_interrupt_init();
 //MCF_UART0_UIMR = 0;
 //MCF_UART1_UIMR = 0;
 MCF_UART2_UIMR = 0;
 
 /*
 * Calculate baud settings
 */
 ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));

 MCF_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
 MCF_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
 MCF_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
 MCF_UART1_UBG2 = (uint8)(ubgs & 0x00FF);
 MCF_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
 MCF_UART2_UBG2 = (uint8)(ubgs & 0x00FF);

 /*
 * Enable receiver and transmitter
 */
 MCF_UART0_UCR = (0
  | MCF_UART_UCR_TX_ENABLED
  | MCF_UART_UCR_RX_ENABLED);
 MCF_UART1_UCR = (0
  | MCF_UART_UCR_TX_ENABLED
  | MCF_UART_UCR_RX_ENABLED);
 MCF_UART2_UCR = (0
  | MCF_UART_UCR_TX_ENABLED
  | MCF_UART_UCR_RX_ENABLED);

}
/********************************************************************/
// this function was added by ylkoh
void
uart0_interrupt_init(void)
{
 MCF_INTC1_ICR13 |= 0x3F;      // 111 111 => IL + IP
            // (Interrupt level + Interrupt priority)
 MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK13 + MCF_INTC_IMRL_MASKALL); // refer to UM Interrupt Sources ch.15.3.6.1
 
 MCF_UART0_UIMR |= (0
     | MCF_UART_UIMR_TXRDY
     | MCF_UART_UIMR_RXRDY_FU);
     //| MCF_UART_UIMR_DB
     //| MCF_UART_UIMR_COS);
  
}
void
uart1_interrupt_init(void)
{
 MCF_INTC1_ICR14 |= 0x3F;      // 111 111 => IL + IP
            // (Interrupt level + Interrupt priority)
 MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK13 + MCF_INTC_IMRL_MASKALL); // refer to UM Interrupt Sources ch.15.3.6.1
 
 MCF_UART1_UIMR |= (0
     | MCF_UART_UIMR_TXRDY
     | MCF_UART_UIMR_RXRDY_FU);
     //| MCF_UART_UIMR_DB
     //| MCF_UART_UIMR_COS);
  
}

 Can you help me find out what happen?

 Thanks in advance.

Regards,

YL Koh

[Nouchi]

hello YL Koh,

Did you think to enable interrupts by setting the right level (usally to 0) to the 'I' field in SR CPU core register ?

Emmanuel