Hello, i want to interface two peripheris at the microco...

[arneschmidt79]

Hello,

i want to interface two peripheris at the microcontroller mcf52223. An ADU and a memory chip.
The QSPI generate the  chip selct signal  to start the conversion of the ADU in wrap around modus.
Data were only read from the ADU. The QSPI write only any data (no ADU data) to the memory chip.

cs0 start conversion ADU  and cs1 select memory chip to write.

I want to use each peripheri at the same time: write Datat to memory and read Data from ADU

Can I send cs0 and cs1 signals at the SAME  time to the ADU and memory chip?

Thanks for help.

[JimDon]

I doubt you can get both CS lines to go low at the same time but you can just use a GPIO line to control one of the chips.

[mjbcswitzerland]

Hi

The QSPI has a mode where the 4 outputs are used to control a 4-to-16 expander. Therefore it is possible to program it to assert 2 lines at the same time. Controlling two GPIOs is however usually easier to do in general purpose applications.

Whether it will be possible to write to one and read from another at the same time is another question - probably both chips will drive their MISO line so some buffering (diode-OR, Open-Collector-AND) will probably be necessary. Then it depends on the protocol for each chip whether it is possible to set them up (sending commands) to get them to accept data and return data in the same frame.

Regards

Mark

www.uTasker.com

[Kremer]

You can put all CS low at the same time if you want. Just set the QSPI_CS field on QDR as you wish. If you make QSPI_CS field equal to 0, all 4 chip select lines will go low at the same time, since each bit controls the state of each one of the 4 lines.
So, to activate low CS0 and CS1 at the same time, just make QSPI_CS filed as 0x0C and it´s done.

Message Edited by Kremer on 2008-07-21 04:34 PM

[admin]

As answered Kremer , "You can put all CS low at the same time if you want. Just set the QSPI_CS field on QDR as you wish."

  Check the following detail. The remaining QSPI lines are shared. There is no problem, if ADC is triggered by its CS active, with its DIN ignored and its DOUT HiZ. Else, the ADC will conflict with another simultaneously selected device.

  In the later case, it is much easier to select only one device at a time. If you still with to overlap the two devices, you will need to learn the specific ADC protocol to understand, which exactly input bits are still ignored and which exactly output bits are HiZ.

[yosida]

I am also facing the same problem. I am giving 3 chip select lines to the external decoder.  The decoder will convert the 3 chip select lines in to 7 chip select lines. Hence, I want to control the  either 1 or 2 or all 3 chip select lines simultaneously. Could you please let me know how I can do that. I am attaching the code what I am using at present. When I execute the below mentioned code then all the 3 CS lines are drawn simultaneously. This is an issue because in this case i cannot output the combination 011. Could you please let me know how can I solve the problem

   param = QSPI_CS3;// QSPI_CS1;
   printf ("Setting Chip select as CS3, CS2 and CS0 to %d ... ", param);
   if (result == ioctl (fd, IO_IOCTL_QSPI_CHIP_SELECT, &param))
   {
      printf ("OK\n");
   } else {
      printf ("ERROR\n");
   }
  
 param = QSPI_CHIP_SELECT_SET_0;
 ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, &param);

   param = QSPI_CS2;
   printf ("Setting Chip select as CS3, CS2 and CS0 to %d ... ", param);
   if (result == ioctl (fd, IO_IOCTL_QSPI_CHIP_SELECT, &param))
   {
      printf ("OK\n");
   } else {
      printf ("ERROR\n");
   }

 param = QSPI_CHIP_SELECT_SET_0;
 ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, &param);

   param = QSPI_CS0;// QSPI_CS1;
   printf ("Setting Chip select as CS3, CS2 and CS0 to %d ... ", param);
   if (result == ioctl (fd, IO_IOCTL_QSPI_CHIP_SELECT, &param))
   {
      printf ("OK\n");
   } else {
      printf ("ERROR\n");
   }

 /* Bring CS low test*/
 param = QSPI_CHIP_SELECT_SET_0;
 ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, &param);

   /* Bring CS high */
 param = QSPI_CHIP_SELECT_SET_1;
 ioctl(fd, IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE, &param);

[admin]

yosida,

at the register level, you need to fill bits QSPI_CS (11-8) of the related QCR entries with the desired values.

Example: Need to pulse low CS0 during each transfer, and to pulse low CS1 during entry 7 and entry 15.

Passive CS is high level. First transfer at entry[0]. Last transfer at entry[15].

The needed values of QCR[0-15] bits:

QAR    CONT    QSPI_CS

---------------------------------------------------

0x20   0       0xE

0x21   0       0xE

0x22   0       0xE

0x23   0       0xE

0x24   0       0xE

0x25   0       0xE

0x26   0       0xE

0x27   0       0xC

0x28   0       0xE

0x29   0       0xE

0x2A   0       0xE

0x2B   0       0xE

0x2C   0       0xE

0x2D   0       0xE

0x2E   0       0xE
0x2F   0       0xC

Message Edited by yevgenit on 2009-09-08 04:11 PM

[yosida]

Hi Yevgenit

I am using the Freescale MQX RTOS Version 3.2. The Target processor is MCF52259 Cold fire 2 family. I want to use the external 3 to 8 decoder. The input to the external decoder will be CS0, CS2 and CS3. The output of the decoder will be the 7 chip selects based on the combination of the input chip selects For example.

CS3 CS2 CS0 Device

0     0      0     no Device Select

0     0      1      Device 1

0     1      0      Device 2

0     1      1      Device 3

1     0      0      Device 4

1     0      1      Device 5

1     1      0      Device 6

This functionality can only be achieved when I am able to control the chip selects pins simultaneously and change the status of the pins depending on the chip select line. I want to do it using MQX RTOS IOCTL routines.

Thanks

Atul

[admin]

yosida ,

I am not familiar with MQX RTOS IOCTL routines. But, I believe, your API permits writing into QSPI registers.

Let CS outputs of QSPI controller are tied to the following address inputs of the regular 3-to-8 decoder: CS3 is tied to A2 input, CS2 is tied to A1 input,  CS0 is tied to A0 input

The value is need to be filled into QWR[CSIV]: 0

The values are need to be filled into QCR:

QAR    entry    CONT    QSPI_CS[3]    QSPI_CS[2]    QSPI_CS[1]    QSPI_CS[0]    selected

---------------------------------------------------------------------------------------

0x20   0          0         0                   0                  -                  0                  none

0x21   1          0         0                   0                  -                  1                 device1

0x22   2          0         0                   1                  -                  0                 device2

0x23   3          0         0                   1                  -                  1                 device3

0x24   4          0         1                   0                  -                  0                 device4

0x25   5          0         1                   0                  -                  1                 device5

0x26   6          0         1                   1                  -                  0                 device6

Note: above example isn't tested with actual hardware.