DDR RAM problem after lowering fsys of MCF5275

[Inky]

Hello,

we've tried to lower the fsys from 150MHz to 75MHz and the system will hang when it tried to copied data from the flash to the RAM and execute it. we're using u-boot and it works just fine when fsys is set within 100MHz and 150MHz. however, it hanged when we set the fsys to 75MHz or lower.

we only modified the the MFD & RFD in SYNCR while switching the fsys. so, we wonder if there's something else we need to modify?

- Inky Lung

[macl]

Hi,

  I don't know all the details but I think that 75MHz is too slow for the DDR.  I think the minimum frequency is 83MHz.

Mac 

[taigbr]

Hi Inky,

during startup I am setting up the pll from low speed to 150MHz
in several steps. Somewhere in between I also use 75 MHz and wait
for the PLL to lock. It doesn't seem to matter to the DDR RAM.
Maybe your PLL values produce an overshoot of frequency
or you don't wait for the PLL to lock.
Kind regards,
Georg Brechlin

[Inky]

Hello Georg,

i'm using the following code during setup of the fsys and check the D3 of the SYNSR if the PLL is locked. the system will boot if i set the fsys to 100MHz, 125MHz or 150MHz while it hanged (at the point when the system tried to load the data from the NOR Flash to the DDR SDRAM) if i set it to 50MHz or 25MHz. and, indeed, i tried this in the M5275EVB.

void cpu_init_f (void)
{

        unsigned long *aux = (unsigned long *) (MCFSIM_SYNSR);

        /* Disable Software Watchdog Timer */
        mbar_writeShort(MCFSIM_WDT_WCR, 0x0000);

        /* Set PLL */
//      mbar_writeLong(MCFSIM_SYNCR, 0x01000000);  /* 150 MHz clock */
//      mbar_writeLong(MCFSIM_SYNCR, 0x03080000);  /* 125 MHz clock */
//      mbar_writeLong(MCFSIM_SYNCR, 0x00000000);  /* 100 MHz clock */
        mbar_writeLong(MCFSIM_SYNCR, 0x00080000);  /* 50 MHz clock */
//      mbar_writeLong(MCFSIM_SYNCR, 0x00100000);  /* 25 MHz clock */
        while (! ((*aux) & 0x00000008) );          /* wait for PLL lock */

        /* set SCM RAMBAR */
        mbar_writeLong(MCFSIM_SCM_RAMBAR, 0x20000200);

        /* Set up GPIO pins for use UART 0 & 1 */
        mbar_writeShort(MCFSIM_GPIO_PAR_UART, 0x3FFF);

        /* Enable Ethernet pins */
        mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
        mbar_writeByte(MCF_GPIO_PAR_FEC0, CFG_FEC0);


        /* CS0 - AMD Flash */
        mbar_writeShort(MCFSIM_CSAR0,0xffe0);      /* start at first MB of 2. */
        mbar_writeShort(MCFSIM_CSCR0, 0x1980);     /* WS=0110 (6 wait states), AA=1, PS=10 (16bit port) */
//      mbar_writeLong(MCFSIM_CSMR0, 0x001f0001);  /* 2MB of flash, WP=0, V=1 */
        mbar_writeLong(MCFSIM_CSMR0, 0x003f000f);  /* 4MB of flash, WP=0, V=1 */
                /* 16-31 bits for mem size. set 8 bit for write protect. set bit 0 for valid CS */

        /* Not used CSs */
        mbar_writeLong(MCFSIM_CSMR1, 0x00000000);
        mbar_writeLong(MCFSIM_CSMR2, 0x00000000);
        mbar_writeLong(MCFSIM_CSMR3, 0x00000000);
        mbar_writeLong(MCFSIM_CSMR4, 0x00000000);
        mbar_writeLong(MCFSIM_CSMR5, 0x00000000);
        mbar_writeLong(MCFSIM_CSMR6, 0x00000000);
        mbar_writeLong(MCFSIM_CSMR7, 0x00000000);

}



Message Edited by Inky on 2007-09-28 03:08 AM

Message Edited by Inky on 2007-09-28 03:10 AM

[taigbr]

Hi Inky,

before I do any changes in the SYNCR, I wait for the lock status:
Something like:

while (! ((*aux) & 0x00000008) );          /* wait for PLL lock */

mbar_writeLong(MCFSIM_SYNCR, 0x00080000);  /* 50 MHz clock */

while (! ((*aux) & 0x00000008) );          /* wait for PLL lock */

But maybe the compiler is doing the trick. Try to declare the aux as pointing
to a volatile value.
Kind regards,
Georg Brechlin

[Inky]

Hi Georg,

We tried both
- change to volatile
- do a pll lock wait
, but it still doesn't work.

May I ask what boot loader and compiler are you using in order to get 50MHz to work?  Thanks.

-Andrew

[taigbr]

Hi Andrew,

when I started with my board, I didn't dare to take it to full speed and left
it running at low speeds. But that was at the time when there where lots
of mistakes in the MCF5257 user manual regarding DDRAM.
Did you think about the changes in all the DDRAM configuration?
Like the refresh count and all the rest that have to fit to the new
clock setting. Maybe your RAM just isn't refreshed in time.

Best regards,
Georg

[Inky]

Basically we use the same ddr as evb to test our board, so I doubt it is the setting problem.  On the other hand it is very likely to be the layout problem.  Hopefully it will be fixed in the next revision.  Thanks for your help.

-Andrew

[taigbr]

Hi Andrew,

what I meant (and probably didn't make clear enough)
that you have to change RCNT in the coldfire registers
and also in your command file. If you lower the frequency
you have less refresh cycles to the DDR RAM and it will
forget its contents. Maybe other values have to be
adapted too.
Best regards,
Georg