Sorry, but that's not right.
ColdFire and 68K use the same opcode encodings - and hence the same instruction widths - where the same instruction exists in both architectures.
Freescale describe the ColdFire architecture as a 'variable-length reduced instruction set (RISC) architecture'. Standard RISC implementations tend to use a fixed width of 2 or 4 bytes per instruction, (although both PowerPC and ARM slightly muddy that distinction) whereas ColdFire uses 2, 4 or 6 bytes depending on the instruction.
What Freescale actually did when designing ColdFire was to trawl through the 68K instruction set removing overly-complex instructions that were too difficult to implement efficiently in a redesigned RISC-like processor core.
One of the differences between ColdFire and more traditional RISC implementations is that ColdFire supports memory-based operands. You can add a register to a memory location in a single instruction, whereas RISC processors would normally need three (load from memory, add, store back to memory).
The word RISC has a debatable meaning nowadays anyway. The PowerPC is definitely considered as a RISC processor, but it has far more instructions that ColdFire.
