Can someone explain Interrupt Levels and Priorities

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Can someone explain Interrupt Levels and Priorities

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WOLF
Contributor I
I am using the Eport interrupts on a design, and I dont fully understand Priorities and Levels.  I see in the Reference manual that they have a preset/Unchangeable Priority.  but what about level?  how does it all work together.   how does level and priority relate to interrupt servicing?
 
 
Thanks in advance,
 
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admin
Specialist II
This is easy.
Imagine that the CPU is servicing an interrupt with level N. Then an interrupt request with level M activates. If M>N then the CPU will start processing the new interrupt, otherwise it will finish processing the first interrupt before starting to process the next. That's how levels work. Level 7 is special, the above doesn't apply to it.
Now imagine that there are several pending interrupt requests with the same level. That's where priorities come in. The one with the highest priority will be serviced first, others will wait. Then if a new interrupt request activates with the same level and a higher priority, it will still wait. Unlike levels, priorities do not preempt each other.
EPORT is special: it has a 'fixed midpoint priority' between 3 and 4. You can think of it as having priority 3.5. The interrupt level is still configurable, though.
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admin
Specialist II
Thank you, Georg, for correcting me. I wasn't too careful reading the manual. Of course, EPORT's interrupt level is not configurable. Looking into the manual for my MCU (MCF52233), I cannot see which level is used by EPORT.
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taigbr
Contributor I
Hi Scifi,

take a look at:
http://www.freescale.com/files/32bit/doc/ref_manual/MCF5275RMAD.pdf?fpsp=1
I don't know if this scheme works for all coldfire mcus.
Regards, Georg


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WOLF
Contributor I
Thank you both, this has help me to understand them.. 
 
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taigbr
Contributor I
Hi Wolf,
there is a nice picture in the ref manual addendum for the 5275 showing the
priority levels. But it states that the eport ints are of mid priority, but all with
a different int level. Irq5 is level 5 and mid priority, Irq1 is level 1 and mid priority.
They are not all allocated at level 3.
Regards, Georg
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JimDon
Senior Contributor III
Simply stated, a level has a priority, and then with in that level there is a "sub-priority" called the "priority".

Levels can be locked out, but once a level is enabled all devices on that level will be serviced based on the priority within the level.

You should say which chip, as different ones have different ways you can address this.
Some chips you can set both the level and priority others no.



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