Byte writes to word addressable Static RAM

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Byte writes to word addressable Static RAM

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timw
Contributor I

I have a prototype board where the static RAM is only word addressable (A0 is not connected). I can't do byte writes. Is there any way of configuring a MCF5329 so that, for a byte write, it first reads the word, then puts the new byte in the appropriate byte and then writes the modified word back?

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TomE
Specialist II

> I have a prototype board where the static RAM is only word addressable

 

Shoot the hardware designer. Smiley Happy

 

> Is there any way of configuring a MCF5329 so that, for a byte write, it first

> reads the word, then puts the new byte in the appropriate byte and then

> writes the modified word back?

 

My first answer was "no", but then I thought about it a bit and it should be possible.

 

The MCF5329 runs terribly slowly if you don't enable the cache, so I'm assuming you do have the cache enabled.

 

This makes DMA a little more complicated, but that's one of the things you have to deal with.

 

All you need to do to get around your problem is to map the SRAM with an ACR in COPYBACK mode:

 

MCF5329 Reference Manual, Rev 35.3.3.3 Copyback ModeWrite accesses to regions specified as copyback that hit in the cacheupdate the cache line ... without an external bus access.... If a byte, word, longword, or line write access missesin the cache, the required cache line is read from memory...... When a miss selects a modified cache line forreplacement, the modified cache data moves to the push buffer...push buffer contents are then written to memory.

 

That will do what you want, except it will read 16 bytes for every write (byte, word or long) and will only write the data back when that cache line is reused for something else. If you are performing DMA from that memory you'll have to execute "CPUSHL" instructions for every cache line in the DMA block. If you are performing DMA to that memory you'll need to CPUSHL with "invalidate" set before starting the DMA. DMA is a bit easier if you use WRITETHROUGH mode, but you can't do this with that miswired SRAM.

 

Depending on the software architecture and the use it might be easier to force your code to always access that memory through function calls or macros that perform the RMW as required. Can you treat that memory as an array of words or as a "file store"?

 

I hope you're not wanting to use the SRAM for the LCD Controller as a video buffer. That works far better with the memory in WRITETHROUGH mode, but you can't do that with your hardware if you want to use byte writes.

 

If you don't need all the SRAM you can always configure the Flexbus for that address range in byte-wide mode. That means you'd be using only half the memory at half the speed, but it would work without software changes.

 

Tom

 

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TomE
Specialist II

> I have a prototype board where the static RAM is only word addressable

 

Shoot the hardware designer. Smiley Happy

 

> Is there any way of configuring a MCF5329 so that, for a byte write, it first

> reads the word, then puts the new byte in the appropriate byte and then

> writes the modified word back?

 

My first answer was "no", but then I thought about it a bit and it should be possible.

 

The MCF5329 runs terribly slowly if you don't enable the cache, so I'm assuming you do have the cache enabled.

 

This makes DMA a little more complicated, but that's one of the things you have to deal with.

 

All you need to do to get around your problem is to map the SRAM with an ACR in COPYBACK mode:

 

MCF5329 Reference Manual, Rev 35.3.3.3 Copyback ModeWrite accesses to regions specified as copyback that hit in the cacheupdate the cache line ... without an external bus access.... If a byte, word, longword, or line write access missesin the cache, the required cache line is read from memory...... When a miss selects a modified cache line forreplacement, the modified cache data moves to the push buffer...push buffer contents are then written to memory.

 

That will do what you want, except it will read 16 bytes for every write (byte, word or long) and will only write the data back when that cache line is reused for something else. If you are performing DMA from that memory you'll have to execute "CPUSHL" instructions for every cache line in the DMA block. If you are performing DMA to that memory you'll need to CPUSHL with "invalidate" set before starting the DMA. DMA is a bit easier if you use WRITETHROUGH mode, but you can't do this with that miswired SRAM.

 

Depending on the software architecture and the use it might be easier to force your code to always access that memory through function calls or macros that perform the RMW as required. Can you treat that memory as an array of words or as a "file store"?

 

I hope you're not wanting to use the SRAM for the LCD Controller as a video buffer. That works far better with the memory in WRITETHROUGH mode, but you can't do that with your hardware if you want to use byte writes.

 

If you don't need all the SRAM you can always configure the Flexbus for that address range in byte-wide mode. That means you'd be using only half the memory at half the speed, but it would work without software changes.

 

Tom

 

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TomE
Specialist II

The other (obvious but silly) software workaround would be to write all your software in C++ and overload the assignment operator for the SRAM memory Class to handle this.

 

If you were using an MCF54xx you could enable the MMU and trap all accesses to the SRAM to go via a fixup handler.

 

It may still be worth fixing the hardware to give you byte-write support. These software fixes generate all sorts of complexities and bugs bugs later on.

 

Tom

 

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timw
Contributor I

Thanks, I'll try the cache thing.

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