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BDM minimum connection

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LPs1978
Contributor III

Hi all,

   I found that there is a possible minimum connection for the ColdFire BDM, as listed below:

 

VDD
GND
ALLPST (connected to all four PST[3:0] signals)
PSTCLK
DSI
DSO
DSCLK
/RSTI
/BKPT
If using something other than the P&E wiggler, you don't need the ALLPST and PSTCLK signals.

 

This allow the debugging but not the tracing.

 

I think that this connection allow to set software and hardware breakpoints, to dump the ram and CPU registers.

What are the not allowed features?

 

Thanks in advance

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Obetz
Contributor III

the Coldfire uC doesn't need PSTCLK and ALLPST for debugging, but the debugging interface hardware (e.g. P&E) might require the clock signal or PST or both.

 

Oliver

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LPs1978
Contributor III

Hi all,

   probably I found out the answer: I analyzed the 52221DEMO board schematics where the BDM seems to be connected with the "reduced style".

 

 

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LPs1978
Contributor III

Thank you for your reply, but brobably I wasn't so clear in my question, because of my bad english.

 

I want to use a P&E coldfire BDM, but I want to reduce the number of pins used for debugging.

 

What I'm asking is: what are the debugging features that are not supported with the reduced connection (listed in the first post) using CodeWarrior and a ColdFire V2?

 

Need I a different driver for the P&E BDM to work with the reduced connection?

 

 

 

 

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ChrisJohns
Contributor I

Almost correct. You may need the PST signals to detect when the processor halts but that depends on the driver on the host handling the BDM protocol and the type of Coldfire.

 

The BDM driver such as the one in the BDM package on Sourceforge can manage the CSR halt bit and detect the CPU has halted with out the PST signals. This register is clear on read. I developed the code to handle this as the 5206e had multi-function PST/IO pins and I had used the pins for IO. Not long after this and now many years ago Greg Ungerer reported to me 5307 problems. I found a race condition in the hardware where the halt bit was not returned in the BDM request and the CSR register was still cleared. The halt event was missed.

 

So the lesson is simple. Check any changes you make very carefully to make sure they work.

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