Allowed input Jitter on MCF54455

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Allowed input Jitter on MCF54455

377 Views
michaelnoel
Contributor I

I am using a spread spectrum clock on the MCF54455 to reduce emissions.  We tried it at 2% variation, and the processor did not work. It works and solves our problem at 0.5% jitter, but I cannot find jitter specification in the data sheet. What are the jitter specs, so that I can be confidant that this solution will not cause field failure of our product?

Thanks

Labels (1)
0 Kudos
1 Reply

277 Views
TomE
Specialist II

It is a digital PLL and none of the Data Sheets or Reference Manuals detail the design well enough to be able to know what the limits are. I don't think you can get a specification to design from for this.

In the Data Sheet it gives values for "Frequency un-lock range" and "Frequency lock range" (of +-4% and +-2% of Fsys respectively), but I have no idea what that really means in practice.

I don't think the percentage deviation is a problem. The critical thing would be how fast the input frequency changes before the PLL fails to track it and loses lock. That depends on the PLL filter characteristics - which aren't documented. So the critical thing is the oscillator deviation multiplied by the modulation frequency.

In the Errata, "SECF034: PLL Loss-of-lock at Large Voltage Differentials" says that there was a problem in early silicon where the PLL lost lock. It said that could be worked around by "disabling the PLL's loss of lock feature". So you may be able to do that to continue your experimentation.

The CPU probably didn't work because the PLL never locked, or kept dropping out of lock and resetting the CPU.

Read the details on how the chip detects lock in "8.3.2 Lock Conditions". Also note that when not locked the PLL frequency may exceed the maximum allowed, which is why they recommend resetting the CPU when lock is lost.

What mode are you starting in? You should probably start in non-PLL mode. That would at least let you monitor the PLL lock condition and report it as you test different input clock modulation frequencies and deviations.

I don't think you can use USB if you're dithering the clock. It has a tight frequency specification. Ethernet is also sensitive to this, but as long as you're using a non-dithered clock source for the Ethernet PHY it should be OK.

Tom

0 Kudos