5329 Cache configuration

[timw]

I am using a 5329 with two 64 MB SDRAMs. The documentation on the cache Access Control Registers is ambiguous. How would I set the mask bits? What is the maximum address space for an Access Control Register?

[TomE]

> The documentation on the cache Access Control Registers is ambiguous.

Please provide details on HOW you think it is ambiguous.

Provide section numbers from the manual, and cut/paste sections of text in to your reply. Pasting them in "as code" (using the "Insert Code" button) helps to make it clear what you are quoting.

> 5329 with two 64 MB SDRAMs ... How would I set the mask bits?

How do you have the SDRAMS connected? They could be 16 bit SDRAMS running from the one chip select or they could be 32-bit chips running from two chip-selects. There are other possibilities. What addresses do you have them programmed to?

> How would I set the mask bits?

You set the mask bits to "cover" the address range of the memory region you want that ACR to apply to.

Table 5-3. ACRn Field Descriptions31–24 Address BaseAddress base. Compared with address bits A[31:24].Eligible addresses that match are assigned the accesscontrol attributes of this register.23–16 Address MaskAddress mask. Setting a mask bit causes the correspondingaddress base bit to be ignored. The low-order mask bitscan be set to define contiguous regions larger than16 Mbytes. The mask can define multiple noncontiguousregions of memory.

I would guess a possible ambiguity would be to ask whether the "corresponding address base bit" for bit 16 is Address line A16 or A24. If it masked A16 then the "block size" would be 64k. If it masked A24 then the block size would be 16M. That matches the above description, so the Address Mask bits correspond 1:1 with the Address Base bits.

64M is 4 times 16M so the bottom two mask bits should be set to match a 64M space. If your two 64M SDRAM chips are in a 128M block, then that's 8 times 16M so the bottom three mask bits should be set for the one ACR to match the entire region.

Note that the way you program this in the MCF5329 is to set up the CACR with a "default" for all of memory, then set up the ACRs to the "exceptions" to that default.

The options break down to:

1 - Set up the CACR to default to "Cache OFF" and then set up ACRs to cache your RAM, or

2 - Set up the CACR to default to "Cache ON" and then set up one ACR to "Cache OFF" for the I/O page and another one to "Cache OFF" to cover any FLASH that you might want to write to.

Another option would be to have ACR1 covering the entire SDRAM with cache enabled, but then to have ACR0 overlapping 16M of the same memory with the cache disabled. That would give you 16M to use for DMA Buffers without having to worry about cache flushing and so on.

Tom