T2080 : RCW Memory Ratio Configurations

[Arathi]

Hi NXP Support Team,

I am having T2080 custom board with SYSCLK and DDRCLK configured to 133.3 MHz, and cfg_rcw_src[8:0] boot pins are configured with value 0xF2.

When I am trying to load harcoded RCW MEM_PLL_RAT is supposed to be 11:1 as per Table 4-16 of T2080 Reference Manual but I am unable to find 11:1 option from RCW configuration Window dropdown

But when I am trying to read RCWSR1 register from init_sram.tcl file I am getting MEM_PLL_RAT as 11:1.

Can you please confirm what should be the exact value of MEM_PLL_RAT as per my configurations.

Thanks,
Arathi

[yipingwang]

Please refer to "MEM_PLL_RAT" configuration in "Table 4-14. RCW Field Descriptions"

This field selects the DDR data rate to DDRCLK
ratio
Options:
Binary Decimal DDR data rate /
DDR REF CLK
frequency
00_0100 4:1 8:1
00_0101 5:1 10:1
00_0110 6:1 12:1
00_0111 7:1 14:1
00_1000 8:1 16:1

00_1001 9:1 18:1
00_1010 10:1 20:1
00_1100 12:1 24:1

All other encodings are reserved.

Please configure MEM_PLL_RAT in your RCW as 12:1 rather than 11:1.