Hello Senthilkumar R,
In the above scenario, the LAW and MMU TLB configuration in CW initialization file will affect the following u-boot execution. In PowerPC architecture, after the target resets, u-boot starts executing in the 4K boot page range at 0xFFFFF000, this default TLB entry is configured by hardware. It is recommended to run and debug u-boot from NOR/NAND/SPI flash or SD card, then follow the application note CodeWarrior U-Boot Debugging to debug u-boot.
If you still want to debug u-boot from DDR RAM, please try this method.
Please modify CONFIG_SPL_TEXT_BASE as 0x11001000 in include/configs/P1022DS.h, then rebuild u-boot image, and download the image P1022DS_SDCARD_config/u-boot-with-spl.bin to DDR RAM.
Please custom the CW initialization file to only keep CCSR and DDR LAW and TLB configuration sections, after download the u-boot image to DDR, please clear CCSR TLB configuration from CodeWarrior IDE, only including TLB configuration for DDR memory to execute the code from DDR.
Have a great day,
Yiping
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