MPC8548E bring up

[sdsp]

Hi,

We at SDSP designed a new PMC/XMC quad ADC card with a xilinx virtex-5 FPGA and MPC8548E core.

http://www.sundancedsp.com/products.php?action=detail&param=89

I am trying to bring up the MPC using a USB tap and am getting the foloowing error

CCSProtocolPlugin: Failed to reset the target

[Draco/m HIP8: ELF is not in expected HALT mode]

Can someone tell me how to debug this error?

The config signals are asserted via a CPLD. And these are the values set during HRESET

cfg_sys_pll    <= "0101"         when config='1' else "ZZZZ";   
cfg_core_pll    <= "110"          when config='1' else "ZZZ";   
cfg_rom_loc    <= "110"          when config='1' else "ZZZ";   
cfg_host_agt    <= "111"          when config='1' else "ZZZ";   
cfg_io_ports    <= "111"          when config='1' else "ZZZ";
cfg_cpu_boot    <= '1'            when config='1' else 'Z';   
cfg_boot_seq    <= "11"           when config='1' else "ZZ";   
cfg_pci1_clk    <= '1'            when config='1' else 'Z';   
cfg_pci1_speed    <= '1'            when config='1' else 'Z';   
cfg_pci1_impd    <= '1'            when config='1' else 'Z';   
cfg_pci1_arb    <= '1'            when config='1' else 'Z';   
cfg_pci1_mode    <= '0'            when config='1' else 'Z';   
cfg_gp_input    <= (others => '0')when config='1' else (others => 'Z');   
cfg_srds_en    <= '0'          when config='1' else 'Z';

Config is active for 100 us and 2 sysclks after the HRESET is deasserted. Then all the signals are tristated. The sysclk is running at 100MHz.

Best Regards,

Sdsp.

[sdsp]

Hi Ron,

Thanks for the response. I was able to use the 8548E_SRAM_Flash.cfg to connect to the core and download the simple "hello world" application.

Now when i debug the "hello world" application from the command line, i get the following error

error: couldn't detect command completion (see config debug timeout)

I could not find any help with this error.  Can you please help me figure out what it means.

Regards,

Stephen.

[ronco]

Hi Stephen,

First, make sure you have selected the ROM Version (not the Debug Version) software target of your MPC8548 project, and make sure you are using debug_in_flash.pq38.cfg as your Target Initilization file. 

If you are already doing that then go to the Remote Debugging panel, click Edit Connection then Enable Logging.  Next time you start the debugger you will get a console window displaying status information.  Capture that, along with the text file resulting from selecting Help->About Freescale CodeWarrior->Installed Products->Save As, and create a new Service Request: go to www.freescale.com, click My Freescale, log in if you need to, then click on Enter a Service Request.  Someone here will work with you on resolving this problem.

Regards,

Ron

[ronco]

If you are routing the COP/JTAG signals from the USB TAP to the MPC8548 through the CPLD then make sure that TRST and HRESET are not tied together (they must be able to function independently) and make sure no other agent can assert HRESET during a debug session.  This latter point includes things like WatchDog Timers, master Reset signals, etc.

The CodeWarrior debugger must use a Target Initialization (.cfg) file for this processor, and that file must start with these lines:

# set interrupt vectors

writereg IVPR 0xFFFF0000 # IVPR (compatible to the Flash)

writereg IVOR15 0x0000F000 # debug (a valid instruction should exist to be fetched)

writereg IVOR6 0x0000F700 # program

#######################################################################

# Set a breakpoint at the reset address

writereg IAC1 0xfffffffc

writereg DBCR0 0x40800000

writereg DBCR1 0x00000000

writereg MSR 0x02000200

run

sleep 0x10

stop

writereg DBCR0 0x41000000

writereg IAC1 0x00000000

More initialization may be needed as well depending on what you're trying to do but start with those lines at least.  And if you're not sure that your own Target Initialization file is valid for your board, try using the 8548CDS_sram_flash.cfg file that comes with 8.8 CodeWarrior Dev Studio for Power Architecture.  That file sets up internal SRAM to host downloaded programs and may be a convenient way to get you moving forward.  I hope this helps.

-Ron