Ls1046a Ecc Capture Address

[sanspepin]

I have a baremetal code that injects SBE errors into my DDR memory and generates an interrupts. The error injection and interrupt mechanism works well. However, reading the CAPTURE_ADDRESS & CAPTURE_EXT_ADDRESS registers does not give the expected result.

If I inject an error at address 0x80000000 then the value of CAPTURE_ADDRESS is 0. (seems correct)
If I inject an error at address 0x80000000 then the value of CAPTURE_ADDRESS is 0 (Seem invalid)

If I inject an error at address 0x80000020 then the value of CAPTURE_ADDRESS is 0x20

If I inject an error at address 0xFFFFFFFF then the value of CAPTURE_ADDRESS is 0x7ffffffe0

It seems that bits 4-0 of CAPTURE_ADDRESS are always zero. And precision of the CAPTURE_ADDRESS is in a block of 32 bytes.

Is this normal? and why?
I do my tests on the ls1046afrywy board

[sanspepin]

I made a mistake in my original post. The line:

"If I inject an error at address 0x80000000 then the value of CAPTURE_ADDRESS is 0 (Seem invalid)"

should have been
"If I inject an error at address 0x80000001 then the value of CAPTURE_ADDRESS is 0 (Seem invalid)"

[yipingwang]

For doing up-date the the CAPTURE_ADDRESS register, is it need to clear

the ERR_DETECT register? You need to write '1' to reset bits in the ERR_DETECT.

The address/attributes/data capture registers will capture information for multi-bit ECC errors, single-bit ECC errors, or memory select errors. If a multi-bit ECC error is detected, then the capture registers will update and lock until the ERR_DETECT register is cleared.
If a memory select error is detected, then the capture registers will update and lock until the ERR_DETECT register is cleared.If a single-bit ECC error is detected, then the capture registers will update. They will only lock if the single-bit error counter (in
ERR_SBE) crosses the threshold, setting the single-bit error bit in the ERR_DETECT register. Otherwise, subsequent errors can overwrite the error capture registers. 

[sanspepin]

The ERR_DETECT is clear as you mention at each IRQ event. The problem is that the value return by CAPTURE_ADDRESS is not precise. Bits 0-4 are always zero.  Here is a sample of the code. 

// Read Error
u32ErrDetect = in_be32(DDRCTRL_ERR_DETECT);

//Read Capture Address
u64ErrAddr = (UINT64)(in_be32(DDRCTRL_CAPTURE_EXT_ADDR)) << 32;
u64ErrAddr += in_be32(DDRCTRL_CAPTURE_ADDR);

//Clear Error
out_be32(DDRCTRL_ERR_DETECT, u32ErrDetect);

[yipingwang]

DDR operates in bursts. That means every write/read command will transfer/receive 8 beats, which means 64 bytes for a 64-bit wide interface (or 32 bytes for a 32-bit wide interface). The captured failure address would point to the start of the burst.

Then in the CAPTURE_ATTR[BNUM] you would be able to get the beat number of the 8 beat burst transaction.

Then for a SBE you could decode the ECC syndrome to determine which bit within a 64-bit transaction of a beat (for a 32-bit interface, every two beat would have one ECC byte to decode) has failed.

[sanspepin]

Note: the CAPTURE_ATTRIBUTES return 0x12d02001. If I read this correctly the TSIZ ( transaction size error) report 2 double words or a transaction (or 8 bytes)

If I inject an error at address 0x80000008 then the value of CAPTURE_ADDRESS is 0