Hello lianying zhang,
If the test fails to measure the length of the instruction register, Error measuring IR length is thrown.
The error might be due to one or more of the following reasons:
• TRST stuck low: This may hold the target JTAG logic in reset, preventing any shifts to occur.
• TMS disconnected or stuck: This may prevent the target from making any JTAG state changes.
• TCK disconnected or stuck: This may prevent any state changes or clocking of data.
• TDI disconnected or stuck: This may prevent the test pattern data from getting into the target.
• TDO disconnected or stuck: This may prevent the test pattern data from getting out of the target.
If the test fails, then it is possible that there is a physical connection problem with the JTAG pins, or the JTAG frequency is too high.
Please refer to JTAG interface Connection as the following.
Have a great day,
Yiping
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I have tried the first method, but it is invalid.Then I first show you the ccs log:
hello Yiping Wang,i found that my board's JTAG interface Connection seems to be Incorrect.
The pictures above is from the evaluation board's material.the pwr_hrst_n signal is produced by the MAX6370,right?but unfortunately,my board hasn't the watchdog timer,there are other solutions to make up it or i must add a WDT?
Hello lianying zhang,
In your CCS log , there is no problem to get the configure chain to set up the basic connection to processor, it failed at ccs_reset_to_debug, so I suspected there was problem with HRESET and TRST. COP debugger needs the ability to drive HRESET and TRST independently, please refer to the following timing wave form.
Critical timing for USB TAP is the trailing edge of the HRESET* signal. TRST* must be negated in time for USB TAP to send several COP commands to the processor before HRESET* is negated. Processor control problems occur when the TRST* follows HRESET*.
With TRST* asserted, the JTAG lines are held in reset. This means the JTAG lines cannot be used to send COP commands to the target processor. If the target processor does not receive the COP commands designed to stop when HRESET* is negated, the processor will begin executing target code instead.
So I suggest you check HRESET and TRST according to the above JTAG connection diagram.
Have a great day,
Yiping
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hello,Yiping Wang,The above two pictures are respectively JTAG's interface and cpu.The top picture’s several reset pins（COP_TRST_N,COP_SRST_N,COP_HRST_N） are all connected to PIC Microcontrollers,while cpu's CPU_TRST_N pin is also connected to PIC Microcontrollers,they aren't connected directly to each other.if it is like this,how the jtag can reset the cpu core?it is the reason that leads to" failed to reset the target,core not responding"？Looking forward to your reply！
