Flash Programming Write & Erase fails on QSPI_B

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Flash Programming Write & Erase fails on QSPI_B

990 Views
keithw
Contributor I

On our board design, we have two QSPI Flash Chips (1Gb each) that we will be operating in parallel mode on a LS1046A.  We are using the Flash Programmer utility in Code Warrior (version 11.5.12) to program the devices.  When we program QSPI A flash (Starting Address 0x40000000), everything works as expected.  When we attempt to program QSPI B flash (0x48000000), the data is not written to flash.  We also cannot successfully execute erase commands.  If we program the QSPI B chip using an external device (Corelis JTAG), we are able to successfully read in parallel mode.

Upon investigation of the problem, we instrumented the QSPI Clock, Chip Select, and 4 data lines for the two QSPI chips.  When we issue an Erase command on QSPI A, we see a series of commands go out the QSPI A bus.  I think it’s a status register read, another status register read, a write enable, a status register read, and finally a series of sector erase commands.  This works as expected.

When we issue the Erase command on QSPI B, the same set of commands are sent but the status register read and write enable commands are transmitted out to the QSPI A device while the Erase is sent to the QSPI B device. Since the QSPI B device has not received the WRITE enable command, the Erase does not work.  I’ve attached a scope capture that shows this behavior.

QSPI_B Scope CaptureQSPI_B Scope Capture

Here are the scope signals:

D0 – QSPI_A Clock

D1 – QSPI_A Chip Select

D2 – QSPI_A D0

D3 – QSPI_A D1

D4 – QSPI_A D2

D5 – QSPI_A D3

D6 – QSPI_B Clock

D7 – QSPI_B Chip Select

D8 – QSPI_B D0

D9 – QSPI_B D1

D10 – QSPI_B D2

D11 – QSPI_B D3

Any ideas on what may be going on to cause this behavior?

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9 Replies

803 Views
keithw
Contributor I

@yipingwangHave you heard anything back from the expert team?  Do you need any additional information from me to help figure this out?

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790 Views
yipingwang
NXP TechSupport
NXP TechSupport

I am still working for the update from the expert team now.

I have contacted them again, will update to you as soon as possible.

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yipingwang
NXP TechSupport
NXP TechSupport

Do refer the section 27.7.7 Parallel mode in LS1046ARM to operate the QSPI flash in parallel mode.
Check with the customer if the pin muxing is correctly set in IFC_GRP_[F/E1/D]_EXT RCW field for the QSPI A and B flash. Please Refer to section 3.4.7 IFC, QSPI, FTM and GPIO2 signal multiplexing in LS1046ARM for the same.

We are further investigating the issue on our end.

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750 Views
keithw
Contributor I

If we program the chips using external tools, we are able to boot and read from the parallel flash chips which confirm that the pin multiplexing settings in the RCW are correct.  I have verified these settings.  This issue only appears when programming using the CodeWarrior Flash Programming utility. 

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707 Views
yipingwang
NXP TechSupport
NXP TechSupport

In the following "QSPI Initialization" section in "Target Initialization File", please configure 

QSPI_BFGENCR[PAR_EN] and QuadSPI_IPCR[PAR_EN] as "1".

###################################################################
# QSPI Initialization
###################################################################
def Init_QSPI():
# QSPI_CFG
CCSR_BE_M(0x157015C, 0x20100000)

# SMPR
CCSR_BE_M(0x1550108, 0x00000000)

# QuadSPI_FLSHCR
CCSR_BE_M(0x155000C, 0x00000303)

# Set top address for each device
CCSR_BE_M(0x1550180, 0x44000000)
CCSR_BE_M(0x1550184, 0x48000000)
CCSR_BE_M(0x1550188, 0x4C000000)
CCSR_BE_M(0x155018C, 0x50000000)

# BUF0CR
CCSR_BE_M(0x1550010, 0x00000000)
# BUF3CR
CCSR_BE_M(0x155001C, 0x80000000)
# BFGENCR
CCSR_BE_M(0x1550020, 0x00000000)

# QuadSPI_MCR
CCSR_BE_M(0x1550000, 0x000f4000)

In the following section in "Adds Flash devices for this board" in "Target Initialization File", please configure "address" as 0x48000000.

# Add QSPI device
fl.add_device({"alias": "qspi", "name": "S25FS512S", "address": 0x40000000, "ws_address": 0x10000000, "ws_size": 0x1FFFF, "geometry": "8x1", "controller": "QSPI"})

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keithw
Contributor I

We have made the suggested changes to our target initialization script and are still unable to program the device on QSPI B.  Our target initialization script was configured as you suggested with the exception of QSPI_BFGENCR[PAR_EN] and QuadSPI_IPCR[PAR_EN] as "1".  We added that change and saw the same behavior when attempting to program the QSPI_B flash chip.

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549 Views
yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the following update from the AE team.

Please request the following information from the customer:

1) The connection scheme (schematic) of their design.
2) The scripting file or target initialization file used for initializing the QSPI flash devices. Have there been any changes to this file?
3) Are you able to access QSPI flash devices (A and B) in individual mode and successfully execute the erase command? Can the read and write commands be executed on the QSPI flash device? Please note that in parallel mode, only read commands are supported, whereas in individual flash mode, all supported commands are available. Refer to section 27.6.1 "Serial Flash Access Schemes" in the LS1046ARM for detailed information.
4) Is there a specific reason for using the CodeWarrior Flash Programmer utility to program the QSPI flash devices?

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921 Views
yipingwang
NXP TechSupport
NXP TechSupport

Discussing with the expert team.

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885 Views
keithw
Contributor I

Any updates?

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