ELF is not in expected HALT mode (CDS8548, CW8.7, IDE5.9)

[sai]

When I try to step into next instruction or  somtimes put a break point or do a hard reset from the CodeWarrior IDE I get a message that says:

ELF is not in expected HALT mode or
ELF is not in expected STOP mode

Any idea what this means. Thanks for any inputs.

I'm using USB TAP to connect to target, with a default clock speed of 4.03 MHz.
-Sai

[Black]

I know of at least 2 conditions on a PQIII core which can produce this effect (elf is not in expected halted mode):

1. The core is caught in a recursive exception loop.  Something has caused an exception, and the first instruction of the exception handler also causes an exception, etc.  Some possible causes: local access window for exception handlers is corrupted, TLB entry for exception handlers is corrupted, exception handler location is changed before setting up local access window or TLB entry, or handler code or associated i-cache is corrupted.

2. The core is waiting for a DDR transaction that will never complete.  This can happen when a local access window for DDR is enabled before DDR is initialized.  Any attempted access to DDR memory in this state can cause a hang.

For PQ3 devices it is essential that the Debug Exception vector, IVOR15, be defined and point to a valid address that contains a valid instruction or hardware breakpoints won't work.  And it's a good idea to have the Program Exception vector, IVOR6, also defined this way so software breakpoints will work.

In our 8548 target-initialization files we include lines like these:

# set interrupt vectors
writereg IVPR  0xFFFF0000  # IVPR (compatible to the Flash)
writereg IVOR15 0x0000F000 # debug - (a valid instruction should exist to be fetched)
writereg IVOR6 0x0000F700 # program

# put a valid opcode at debug and progrm exception vector address
writemem.l 0x00000700 0x48000000
writemem.l 0x00001500 0x48000000

I suggest adding these lines to your .cfg file if they are not already there.  Or at least verify the values of IVPR, IVOR6 and IVOR15 before you try stepping.

[sai]

That configuration information was missing in the target initialization file. Once I added those it works fine now stepping into each instruction followed by the reset vector. It does appear once in a while when I click on 'run' and then click on 'break'.

I also tried with the generic.mcp project in the folder "Templates\PowerPC_EABI\StationeryPQ3" and used the target initialization file "PowerPC_EABI_Support\Initialization_Files\PQ3\8548CDS_init.cfg" directory. I noticed the same behavior.

The filename that I installed CW is "CW_Power_Architecture_V8.7_70321"

Thanks for the help.
-Sai


Message Edited by sai on 2007-08-30 07:00 PM

[Black]

Since this issue requires some deeper investigation I would recommend you to submit a service request. Click here to submit a service request.

Please go to your CodeWarrior menu, choose Help->About...->Installed Products->Save as and send us the resulting text file. If you are using a Linux product: Go to <install_dir>/CodeWarriorIDE/CodeWarrior/CodeWarrior_Plugins/Support/Products; You can read the version and build number in the xml files found in this folder; If you downloaded your CW from the web: The archive name contains the build number <ProductName>_<ProductVersion>_<BuildNumber>_pkg.tgz.

Please send us the error message that you get when debugging your project with "Verify Memory Writes" checked and target initialization .cfg file selected in the project's EPPC Debugger Settings panel (please attach also your .cfg file) and the CCS log - in project settings->Remote Debugging->Connection Settings->Edit please check "Enable Logging" before the debug session and send us the log text file.

Also it will be good if you could send an example project or elf file and any other information to help us reproduce the problem.

Thank you.