DDR Validation Tool Tests Description

[athershehzad]

Hello!

I am running a DDR validation test for my custom board based on T1042. 

I want to understand the process of validation that what is actually happening when I run 1write-1read turnaround, 2write-2read turnaround, 4write-4read turnaround, Write then read no turnaround, DMA test, Walking ones and walking zeros tests.

Some of these are passing for my settings and some are failing for one configuration and the same results may fail for the next time and the test that is failing may get pass for the next test in my case. 

So I want to know the working of these tests so that I can review my settings accordingly.

Regards,

Ather

[yipingwang]

Here are the details of DDR validation operational tests.

•        1write-1read turnaround

Runs the hardware built-in memory test. Occurs in several places throughout all of memory area defined by the chip select configuration [CSn_CONFIG and CSn_BNDS registers]. Total write/read streams will be 1 transaction each. The memory controller will check the data during this test. The test fails if memory mismatches are detected. The capture registers will hold information for the transaction that caused the first data miscompare. Note that transactions with ECC errors will take priority in the capture registers.

•        2write-2read turnaround

Runs the hardware built-in memory test. Occurs in several places throughout all of memory area defined by the chip select configuration [CSn_CONFIG and CSn_BNDS registers]. Total write/read streams will be 2 transactions each. The memory controller will check the data during this test. The test fails if memory mismatches are detected. The capture registers will hold information for the transaction that caused the first data miscompare. Note that transactions with ECC errors will take priority in the capture registers.

•        4write-4read turnaround

Runs the hardware built-in memory test. Occurs in several places throughout all of memory area defined by the chip select configuration [CSn_CONFIG and CSn_BNDS registers]. Total write/read streams will be 4 transactions each. The memory controller will check the data during this test. The test fails if memory mismatches are detected. The capture registers will hold information for the transaction that caused the first data miscompare. Note that transactions with ECC errors will take priority in the capture registers.

•        Write then read no turnaround

Runs the hardware built-in memory test. Occurs in several places throughout all of memory area defined by the chip select configuration [CSn_CONFIG and CSn_BNDS registers]. Entire memory will be written before read transactions are issued. The memory controller will check the data during this test. The test fails if memory mismatches are detected. The capture registers will hold information for the transaction that caused the first data miscompare. Note that transactions with ECC errors will take priority in the capture registers.

•        DMA test

DMA is configured using linked descriptors to transfer data from a source address to a destination address in DDR. The size of the data transferred is configurable. The source region is filled with a repeating pattern. After DMA finished the transfer, the test is reading back the data from the destination and compares it with the source data. The test fails at the first mismatch found.

•        Walking ones

Writes a bit pattern that gradually sets [to 1] bits from LSB to MSB. Each byte is written multiple times depending on the selected access size, until each of the contained bits gets set, while the other ones are cleared. For each bit pattern, a write/read/compare sequence is performed. The test is repeated for each of the access size selected using the corresponding access size.

•        walking zeros tests

Writes a bit pattern that gradually clears [sets to 0] bits from LSB to MSB. Each byte is written multiple times depending on the selected access size, until each of the contained bits gets cleared, while the other ones are set. For each bit pattern, a write/read/compare sequence is performed. The test is repeated for each of the access size selected using the corresponding access size.

[athershehzad]

Thanks Yiping,

Can you please identify any problem in my board by looking at the error capture registers value. One more problem is that Sometimes my BIST 1write-1read test gets passed on the same settings and when I run thye test again, it gets failed. What might the possible issue ?

[yipingwang]

Please refer to section "3 DDR4 design checklist" in the application note "AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces - Application Not..." downloaded from "https://www.nxp.com/products/processors-and-microcontrollers/power-architecture/qoriq-communication-...".