Illegal_bp could means almost anything (any unexpected behaviour), but in most of the cases it presents unexpected interrupt.
I have for you few tips for you:
- TCNT register is not writable in normal mode
- You enables 4 output compare interrupts (TC0, TC1, TC2, TC3; command TIE = 0x0F;). If you don’t have defined TC1..TC3 interrupt routines (interrupts 9..11), this will be probably root cause of your issue.
- Commands DisableInterrupts; and EnableInterrupts ; inside interrupt routine is not necessary. I bit is set automatically when MCU enter into interrupt and RTI (return from interrupt) instruction restore I bit during interrupt routine leave.
- Do you have enabled interrupts for CAN modules? Do you have interrupt routines for CAN interrupts?
- Example code below contains Interrupt catcher. This code you can use for detection of unexpected interrupts or directly in your code for handle unexpected interrupts.
volatile unsigned int number_of_ISR = 0;
volatile unsigned char sc0_data_in;
void Unimplemented_ISR(void)
{
asm nop; //insert breakpoint here. If the code stops here, check the "number_of_ISR"
}
#pragma CODE_SEG NON_BANKED
interrupt 1 void ISR_1 (void) {number_of_ISR = 1 ; Unimplemented_ISR();}
interrupt 2 void ISR_2 (void) {number_of_ISR = 2 ; Unimplemented_ISR();}
…//please fill
interrupt 19 void ISR_19 (void) {number_of_ISR = 19 ; Unimplemented_ISR();}
//interrupt 20 void ISR_20 (void) {number_of_ISR = 20 ; Unimplemented_ISR();}
interrupt 21 void ISR_21 (void) {number_of_ISR = 21 ; Unimplemented_ISR();}
…//please fill
interrupt 119 void ISR_119 (void) {number_of_ISR = 119 ; Unimplemented_ISR();}
#pragma CODE_SEG DEFAULT
//==============================================================================
//Example of SCI0 Interrupt routine
//==============================================================================
#pragma CODE_SEG NON_BANKED
interrupt 20 void SCI0_Isr(void)
{
//your SCI routine
}
#pragma CODE_SEG DEFAULT
//==============================================================================