Following is my code for OPWM.
But I am unable to see the OPWM for Channel 1 of eMIOS.
The register values change as per Code Warrior.
How to configure the hardware pin?
Please help.
#include "mpc5674f.h"
void initEMIOS(void);
void initEMIOSch23(void);
void initEMIOSch0(void);
void initEMIOSch1(void);
//void initEMIOSch2(void);
static void FMPLL_init(void)
{
/**** Use for 40 MHz crystal reference ****/
// settings for 264 MHz
SIU.ECCR.B.EBDF = 3; /* Divide sysclk by 3+1 for CLKOUT */
FMPLL.ESYNCR2.R = 0x00000002;
FMPLL.ESYNCR1.R = 0x70040032; // EPREDIV=4, EMFD=0x32=50
while (FMPLL.SYNSR.B.LOCK != 1) {};
FMPLL.ESYNCR2.R = 0x00000001; // ERFD=1
// fextal=40 => fpll = 40*(50+16)/((4+1)*(1+1)) = 264MHz
// fvco = 40*(50+16)/(4+1) = 528 < 600 and > 192 => correct
#if 0
// settings for 200 MHz
SIU.ECCR.B.EBDF = 3; /* Divide sysclk by 3+1 for CLKOUT */
FMPLL.ESYNCR2.R = 0x00000002;
FMPLL.ESYNCR1.R = 0x70040022; // EPREDIV=4, EMFD=0x22=34
// fextal=40 => fpll = 40*(34+16)/((4+1)*(1+1)) = 200MHz
// fvco = 40*(34+16)/(4+1) = 400 < 600 and > 192 => correct
while (FMPLL.SYNSR.B.LOCK != 1) {};
FMPLL.ESYNCR2.R = 0x00000001;
#endif
}
void initEMIOS(void) {
EMIOS.MCR.B.GPRE= 131; /* Divide 132 MHz periphclk by 131+1 = 132 for 1MHz eMIOS clk*/
EMIOS.MCR.B.ETB = 0; /* External time base is disabled; Ch 23 drives ctr bus A */
EMIOS.MCR.B.GPREN = 1; /* Enable eMIOS clock */
EMIOS.MCR.B.GTBE = 1; /* Enable global time base */
EMIOS.MCR.B.FRZ = 1; /* Enable stopping channels when in debug mode */
}
void initEMIOSch23(void) { /* EMIOS CH 23: Modulus Up Counter */
EMIOS.CH[23].CADR.R = 999; /* Period will be 999+1 = 1000 clocks (1 msec) */
EMIOS.CH[23].CCR.B.MODE = 0x50; /* MPC551x, MPC563x: Mod Ctr Bufd (MCB) int clk */
EMIOS.CH[23].CCR.B.BSL = 0x3; /* Use internal counter */
EMIOS.CH[23].CCR.B.UCPRE=0; /* Set channel prescaler to divide by 1 */
EMIOS.CH[23].CCR.B.FREN = 1; /* Freeze channel counting when in debug mode */
EMIOS.CH[23].CCR.B.UCPREN = 1; /* Enable prescaler; uses default divide by 1 */
}
void initEMIOSch0(void) { /* EMIOS CH 0: Output Pulse Width Modulation */
EMIOS.CH[0].CADR.R = 250; /* Leading edge when channel counter bus=250*/
EMIOS.CH[0].CBDR.R = 500; /* Trailing edge when channel counter bus=500*/
EMIOS.CH[0].CCR.B.BSL = 0x0; /* Use counter bus A (default) */
EMIOS.CH[0].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output/trailing clears*/
EMIOS.CH[0].CCR.B.MODE = 0x60; /* MPC551x, MPC563x: Mode is OPWM Buffered */
SIU.PCR[179].R = 0x0600; /* Initialize pad for eMIOS chan. 0 output */
}
void initEMIOSch1(void) { /* EMIOS CH 0: Output Pulse Width Modulation */
EMIOS.CH[1].CADR.R = 250; /* Leading edge when channel counter bus=250*/
EMIOS.CH[1].CBDR.R = 999; /* Trailing edge when channel counter bus=999*/
EMIOS.CH[1].CCR.B.BSL = 0x0; /* Use counter bus A (default) */
EMIOS.CH[1].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output/trailing clears*/
EMIOS.CH[1].CCR.B.MODE = 0x06; /* MPC551x, MPC563x: Mode is OPWM Buffered */
SIU.PCR[180].R = 0x0600; /* Initialize pad for eMIOS chan. 1 output */
}
int main(void) {
volatile int i = 0;
FMPLL_init();
initEMIOS(); /* Initialize eMIOS to provide 1 MHz clock to channels */
initEMIOSch23(); /* Initialize eMIOS channel 23 as modulus counter*/
initEMIOSch0(); /* Initialize eMIOS channel 0 as OPWM, using ch 23 as time base */
initEMIOSch1();
//initEMIOSch2(); /* Initialize eMIOS channel 2 as OPWM, using ch 23 as time base */
/* Loop forever */
for (;;) {
i++;
}
}
