I are new to code warrier and are trying to setup the ability to access external RAM on the address bus.
I are using the softec HCS12x starter kit.
I have set an variable in my code
#pragma DATA_SEG __DPAGE_SEG Bat_RAM
char cExt_RAM;
#pragma DATA_SEG DEFAULT
I are setting cExt_RAM = 0x47.
And then trying to read it and send it back out the serial port (should get ‘G’ on my hyperterminal).
Works if I initialize it in internal ram.
In my startup code I have set Bat_RAM
SEGMENTS /* paged RAM */
BatteryRAM = READ_WRITE 0x200000 TO 0x20FFFF;
END
PLACEMENT
Bat_RAM INTO BatteryRAM;
END
In the map file cExt_RAM is mapped to 0x200000
This sould mean that it is mapped to CS1.
In my startup code I have set the device up as follows.
MODE = 0xA0; // MODC = 1, MODB = 0, MODA = 1 (Normal Expanded Mode)
ECLKCTL = 0x43; // NECLK = 0 (Enabled)
// NECLKX2 = 1 (Disabled)
// EDIV = 3 (Bus clock div 4)
EBICTL0 = 0x34; // ITHRS = 0 (5v Logic levels).
// HDBE = 1 (16b data bus enabled
// Enable Address lines ADDR0:19 + /UDS
EBICTL1 = 0x07; // EWAITE = 0 (External wait Enabled is disabled)
// External Access stretch set to max of 8 cycles.
// alter once working.
MMCCTL0 = 0x0F; // CS0:3 = 1 (Enabled)
MMCCTL1 = 0x05; // EROMON = 1, ROMHM = 0, ROMON = 1
CLKSEL &= 0x7F; // Ensure PLL unsellected
for (i=0; i < 800; i++);
SYNR = 39; // 40 Mhz Bus clock
for (i=0; i < 800; i++);
REFDV = 15; // 40 Mhz Bus clock
for (i=0; i < 800; i++);
while (CRGFLG & 0x08 == 0x08);
CLKSEL = 0x80;
for (i=0; i < 800; i++);
I are experanced with the standard HCS12 but new to the S12x.
As far as I can tell the CS should work.
If I scope CS1 it doesn’t change state. Also the ECLK is not being stretched for the data read/write.
Can you please point me in the right direction.
Regards,
Daniel Rogers
