DMA vs EDMA. increment source/destination adresses in GCT

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DMA vs EDMA. increment source/destination adresses in GCT

348 Views
fasihahmed
Contributor IV

Hey ,

 

Im porting my code from mc56f82748 (uses DMA) to mc56f83763 (uses EDMA).

I can get the DMA to read the first source address data of ADC_0 , but not the next two addresses (which are shown as zero in freemaster). I am trying to read the next  two ADC_1 and ADC_2 samples.

 

from this I think there is something to do with incrementing adresses which is missing in new EDMA. Its it perhaps now called as minor and major loop. 

 

What do I need to choose to have the auto increment in the background so I can also read the next adresses? 

 

My source address is in words so E50Eh is 1CA1C

@xiangjun_rong @ZhangJennie 

fasihahmed_0-1605696832734.png

fasihahmed_0-1605697235432.png

 

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295 Views
fasihahmed
Contributor IV

void GOC_Iphase_DMA_ReInit(void)
{
ioctl(EDMA, DMA_SET_DMA_REQUEST_0, DMA_DISABLE); // Disable peripheral request before modifying DMA registers



/*******************/

/* set values */
ioctl(EDMA_0, DMACH_SET_SOURCE_ADDRESS_OFFSET, 0x0);
ioctl(EDMA_0, DMACH_SET_NBYTES_WITH_MLOFF, -6);
ioctl(EDMA_0, DMACH_SET_SOURCE_ADDRESS_OFFSET, set_source_adress);
ioctl(EDMA_0, DMACH_SET_NBYTES_WITH_MLOFF, nBYTES_value);/* set number of bytes to transfer*/


uw32Address = (UWord32)&(w16IphaseArray[0]);

// set destination address to first member of the structure
ioctl(EDMA_0, DMACH_SET_DESTINATION_ADDRESS, uw32Address<<1 );
ioctl(EDMA_0, DMACH_SET_SOURCE_ADDRESS, 0x1CA1C);

// clear interrupt flag and enable next transfer by writing BCR registers
ioctl(EDMA, DMA_SET_DMA_REQUEST_0, DMA_ENABLE); // Enable peripheral request to initiate the DMA transfer
}

 

i still have issues trying to get all the three current ADC results. I have only the first ADC sample showing up. I have attached my code above for you to get an idea of what im probably missing out?

 

 @xiangjun_rong 

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270 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Fasih,

Because the ADC result register is 0xE50E(Result0), 0xE50F(Result1), 0xE510(Result2),..., so the Result offset should be 2 in Byte.

so

octl(EDMA_0, DMACH_SET_SOURCE_ADDRESS_OFFSET, 0x0);

should be

octl(EDMA_0, DMACH_SET_SOURCE_ADDRESS_OFFSET, 0x2);

Pls have a try.

BR

XiangJun Rong

 

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329 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Fasih,

xiangjun_rong_0-1605772195309.png

For the above screen, I think you need just check the "source minor loop mapping" box, uncheck "destination minor loop mapping" box, furthermore, uncheck the "Channel Linking On Loop Complete"

Because the ADC Result Register is TWO bytes, if you sample 3 ADC channel(sample0/1/2), I suppose that the Minor-loop Offset box should be -6, minor loop in major loop should be +6. Anyway, after the QuickStart configuration, pls check the following Fig:

The SMLOE bit is set, the DMLOE is cleared, the MLOFF bit should be -6(in complementary format), the NBYTES bits should be 6. after you configure the Quick Start tools, if the TCD0_NBYTES_MLOFFYES register is NOT the above value, you have to reconfigure the quick start until it is the value.

Hope it can help you

BR

XiangJun Rong

 

 

 

eDMA_Reg.png

 

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