validation of DDR3 using codewarrior failed

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validation of DDR3 using codewarrior failed

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anshulkhare
Contributor III

Hello,

I am using T2081 and QCVS Codewarrior tool for the validation of DDR3.

While performing the test "Centring the clock" in the validation stage, I was determining the best WRLVL_START byte lane values in which 1/2 clocks of CLK_ADJ have passed for 3/4 clocks of WRLVL_START. While determining the best CLK_ADJ value in the next table as in below image it fails for all conditions including 1/2 clock .

pastedImage_1.png

Could anyone explain why are we facing the above issue.

Thanks in advance!

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ufedor
NXP TechSupport
NXP TechSupport

Which log corresponds to the selected cell?

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