QCVS DDR margin tool

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QCVS DDR margin tool

7,439件の閲覧回数
OneNote
Contributor I

Hi

In our latest codewarriro QCVS, the margin page of DDR validation doesn't have Margin stage as scenarios, only has Diags margin stage. Why this happen? What's the cause?

Thanks.

 

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6,972件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

What processor are you using now?

Which version QCVS tool are you using?

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6,970件の閲覧回数
OneNote-0
Contributor I

Thanks, Yiping.

Processor: LX2160A

QCVS version: 4.23

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6,968件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

Margin stage is removed since QCVS 4.23 2020.11 release.

Margin stage scenario is no longer available for LX2, but is should be available for the rest of devices.

If further information is needed, please feel free to let me know.

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6,965件の閲覧回数
OneNote-0
Contributor I

Thanks.

Further question: how to test margin? use diag margin stage?

 

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yipingwang
NXP TechSupport
NXP TechSupport

I just got confirmation from the development team.

Yes, you should use the diag margin stage.

 

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6,850件の閲覧回数
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Contributor I

Thanks.

Now it's back to 4.22.

There is a new issue happen when run the margin test.

Log attached.

read margin test log.JPG

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6,845件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

Please open CCS console on the right bottom of your task bar, type "log v", then connect to the target board again, the low level CCS log will be printed out.

Please send the CCS console log to me to do more investigation.

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6,840件の閲覧回数
OneNote
Contributor I

ccs.JPG

 

Is this what you want? Thanks.

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6,838件の閲覧回数
OneNote
Contributor I

CCS1.JPG

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6,814件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

It failed at "reset_to_debug". If the RCW is valid, probably there is hardware design problem of the JTAG interface on your custom board.

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6,804件の閲覧回数
OneNote
Contributor I

Measured the reset signals, when nRESET is low, PORESET_B also is low. And also found the HRESET_B is low and keep low always.Is it a clue?

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6,792件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

Would you please refer to "3.2 Working with bareboard application" in the attached document to create a board board project and run it on your target board.

Please click "Target Connections->LX2160A_RDB(1)->Edit->Target Initialization File", 

please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True".

Then connect to the target board, and send CCS console log to me, I just want to check whether the core can be stopped.

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6,782件の閲覧回数
OneNote
Contributor I

Print3.JPG

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6,780件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

Please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True" in CW initialization file and save the configuration.

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6,790件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

Please also try the following commands in CCS console.

delete all

config cc cwtap:<ip>

ccs::config_chain {lx2160a dap}

display ::ccs::get_config_chain

::ccs::stop_multi_core {21}

::ccs::reset_to_debug

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6,786件の閲覧回数
OneNote
Contributor I

Print1.JPGPrint0.JPG

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6,784件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

Please try to run a bareboard application with hard-coded RCW as I mentioned in my previous post.

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6,779件の閲覧回数
OneNote
Contributor I

Print4.JPG

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6,773件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

As I mentioned previously, please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True" in CW initialization file and save the configuration, then run the bareboard application.

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6,808件の閲覧回数
yipingwang
NXP TechSupport
NXP TechSupport

Is it possible to provide your JTAG design schematics for the custom board?

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