jm60: 4mhz clock initilise code for USB

[donw]

I am trying to get a JM60 running with its USB port.bus must be 24mhz, MCGOUT = 48mhz.

my external xtal is 4.00mhz.

Is this initilise code correct?

(Especially Not sure about RDIV = 1 )

            MOV   #$36,MCGC2               
            MOV   #$08A,MCGC1     
_EntryPoint_L1E:   
            BRCLR 1,MCGSC,_EntryPoint_L1E      ; Wait until external reference is stable
_EntryPoint_L21:   
            BRSET 4,MCGSC,_EntryPoint_L21  ; Wait until external reference is selected
_EntryPoint_L24:                         ;Wait until external clock is selected as a bus clock reference
            LDA   MCGSC
            AND   #$0C
            CMP   #8
            BNE   _EntryPoint_L24 ;abs = 0024
 ; 
            MOV   #$3E,MCGC2                  

            MOV   #$08A,MCGC1        
            MOV   #$46,MCGC3 
            BCLR  3,MCGC2       
_EntryPoint_L37:   
            BRCLR 5,MCGSC,_EntryPoint_L37  ; while(!MCGSC_PLLST) Wait until PLL is selected
_EntryPoint_L3A:   
           BRCLR 6,MCGSC,_EntryPoint_L3A ; ;   while(!MCGSC_LOCK) Wait until PLL is locked
                                            
           MOV   #$0A,MCGC1                ; Set MCGC1 register
_EntryPoint_L40:   
           LDA   MCGSC            ;while((MCGSC & 0x0C) != 0x0C) Wait until PLL clock is selected as a bus clock reference
           AND   #$0C
           CMP   #$0C
           BNE   _EntryPoint_L40
                                          ; End of initialization code after reset
           RTS
 

[wrljet]

I use this to setup the JS16 for a 4MHz crystal.  Should be similar (if not the same) on JM60.

// WRL changed to work with 4 MHz xtal, 48 MHz clock for USB

void MCG_Init()
{
    // the MCG is default set to FEI mode, it should be change to FBE mode
    MCGC2 = MCGC2_RANGE_MASK | MCGC2_HGO_MASK | MCGC2_EREFS_MASK | MCGC2_ERCLKEN_MASK;
   
    // loop until the crystal has been initialized                
    while (!MCGSC_OSCINIT);

    // CLKS = 10 to select external reference clock as system clock source
    // RDIV = 111, divide by 128, 4 MHz / 128 = 31.25 kHz, range required by the FLL
    // IREFS = 0, selecting the external reference clock
    //
    MCGC1 = MCGC1_CLKS1_MASK | MCGC1_RDIV2_MASK | MCGC1_RDIV1_MASK | MCGC1_RDIV0_MASK |
        MCGC1_IRCLKEN_MASK | MCGC1_IREFSTEN_MASK;

    // loop until the external reference clock is selected
    while ((MCGSC & 0x1C ) != 0x08);

    // switch to PBE mode from FBE
    // 2b) RDIV = 001, divide by 2, 4 MHz / 2 = 2 MHz, which is the
    //     1 to 2 MHz range required by the PLL.
    MCGC1 = MCGC1_CLKS1_MASK | MCGC1_RDIV0_MASK |
        MCGC1_IRCLKEN_MASK | MCGC1_IREFSTEN_MASK;

    // 2c) PLLS = 1, selects the PLL
    //     VDIV = 0110, multiply by 24, 2 MHz reference * 24 = 48 MHz
    MCGC3 = MCGC3_PLLS_MASK | MCGC3_VDIV2_MASK | MCGC3_VDIV1_MASK;

    // 2e) wait until PLLST is set, indicating source for the PLLS clock is the PLL
    while ((MCGSC & MCGSC_PLLST_MASK) == 0);

    // 2f) wait until the PLL is locked
    while ((MCGSC & MCGSC_LOCK_MASK) == 0);
   
    // switch to PEE mode from PBE mode
    // 3a) CLKS = 00, to select output of PLL as the system clock
    MCGC1 &= MCGC1_RDIV0_MASK | MCGC1_IRCLKEN_MASK | MCGC1_IREFSTEN_MASK;
   
    // loop until CLKST = 11, indicating the PLL output is selected   
    while (MCGSC_CLKST != 3);
}