Vdda on 9S08QE8CLC

[stevec]

I have a microphone audio signal fed into one of the analogue inputs of this uC. The mic feeds into a preamp whose o/p goes to the uC. I have this pre-amp on a separate (lower) supply than the uC supply and so I feed this voltage to the Vrefh/Vdda pin of the uC to maintain it's full dynamic range. However when I power down the mic pre-amp (I power down all external circuits and put the uC into sSTOP3 mode) I find that there is a voltage feeding out of Vdda and powering the mic pre-amp. When all connected up this voltage is 2.0 volts. When disconnected the Vdda pin sits at 2.5 volts (uC Vdd is 3 volts). Is this to be expected? I would rather not have the uC powering other connected circuits. Am I going to have to put Vdda/Vref to Vdd and put up with a reduced dynamic range (my mic circuit is powered by a 1.8V regulator - minimum required for Vrefh/Vdda. It is an 8 bit system at present and I want to get as much fidelity out of it as I can.

[bigmac]

Hello,

Some of your connections are problematic for the particular MCU device.  Vrefh and Vdda are internally bonded together, and similarly with Vrefl and Vssa.  According to the data sheet the maximum differential between Vdd and Vdda, and between Vss and Vssa, is limited to +/- 100mV only.  In practice, this means that each pair of pins requires to be tied together, but using separate bypass capacitors between Vdd and Vss pins, and between Vdda and Vssa pins.

To achieve sufficient resolution for the audio signal, you will usually need 12-bit resolution.  Increasing the ADC resolution will more than compensate for the reduced maximum peak-to-peak volltage level from the pre-amplifier.  To eliminate supply synchronisation issues, the input to the 1.8 volt low dropout regulator should originate from the MCU's 3.3 volt source.

You do not say whether the preamplifier output includes a series coupling capacitor, or not.  If the output is DC coupled, I assume that the quiescent output voltage will be close to 0.9 volt.  In this case, I would suggest that a coupling capacitor be added.

With the use of AC coupling, it is then possible to bias the input of the ADC channel to a voltage of one half of Vcc.  This can be done using a pair of equal value resistors series connected between Vdda and Vssa.  The midpoint of the voltage divider would then connect to both the coupling capacitor and the ADC input.  This will place the quiescent ADC output value close to a value of 2048, to allow for positive and negative excursions from this level.

AC coupling will also help with the supply synchronisation issue in the event that the MCU and preamplifier supplies do not have a common source.

Regards,

Mac

[stevec]

Thanks Mac, I think the data sheet is very ambiguous. I see the 100mV delta value in the electrical characteristics for the ADC. But the data sheet states that for the 16 and 20 pin versions of the chip Vdda amd Vssa are internally bonded to Vdd and Vss. I am using the 32 pin version so thought that this meant I could use a separate voltage for Vdda. I don't see the point in only allowing a 100mV maximum difference. There is no guidance on this. If there were issues regarding use of reference voltages this is usually specifically mentioned (taking separate supply lines from a common point near the voltage source and decoupling close to the chip.) I see that diagramatically this is implied in the refernce manual though.

Thank yoiu for the tip on using the ADC at 12 bits but Istill have to store it at 8 bits. I have not got my head round that yet. It sounds plausible.....

I do not have ac coupling on the o/p of my pre-amp. I am concerned about biasing the ADC input as the resistor chain will have to come off the uC Vdd and thus increase my power down current unless there is no upper limit to resistor value I use (unlikely!). Two 150k resistors will draw 10uA. I don't want to introduce more than that extra current. Even that is a bit too high.

However you have answered my main question. Looks like I have to use Vdd for my reference. But this does raise another problem I am using a 64 Mbit DataFlash chip for speech storage. I have found that when this transfers data from its input buffer to it's main memmory array, it takes a fair amount of current and thus puts a dip on the voltage rail (about 50mV). This is going to transfer to my ADC reference voltage. OK so I need to sort out my decoupling but I have not been able to remove it yet, only mask it's effects! Oh well back to the drawing board.

Steve

[bigmac]

Hello Steve,

For the voltage divider arrangement, use say 22k resistors, but rather than connect directly to Vdd, connect to a GPIO pin configured as an output.  The voltage divider can then be powered down prior to entering stop mode.

For a voice audio signal, the higher ADC resolution is required to handle the dynamic range of the signal - less than the full resolution will suffice for the higher audio amplitudes.  One possible data compression method is to use a quasi-logarithmic conversion approach.  One bit would be required for the sign of the signal, two bits would represent a power of two multiplying factor for the signal amplitude, i.e. 1, 2, 4 or 8.  The remaining bits would then be the most significant five bits of the scaled signal.

The sign and amplitude value would be derived from the raw ADC signal.  The amplitude would have a possible 11-bit range.  However, in your case, the MSB is always likely to be zero because of the limited output from the preamplifier, resulting in an actual 10-bit amplitude range.  Now ignore the LSB, so we are left with a 9-bit amplitude value (0-511), plus sign.

The multiplying factor is represented by n = 0 - 3, and the initial value is 3.

1. If the amplitude is 256, or greater, derive the 5 most significant bits of the current amplitude (right shift by four positions).
2. If the amplitude is less than 256, and n is non-zero, decrement n, and multiply the amplitude by 2 (shift left by one position), and repeat the first step.  If n is zero, derive the 5 most significant bits.

This processing may require use of assembly code for speed.  I assume that your sampling rate would be in the vicinity of 8 kHz.  Finally, the microphone preamplifier may require inclusion of a sharp cut-off 3 kHz lowpass filter to prevent "ailiasing" distortion due to audio components above 4 kHz.

Regards,

Mac

[stevec]

Thanks Mac,

A good tip using the GPIO. Always good to have someone else's perspective on things. I was hoping to not do any processing on the data but looks like I shall need to. We do actually do data compression in most of our products (9 bits to 5) but that is mostly historic when memory was expensive and not very large.

The mic signal has a single pole LP filter on the amplifier section followed by a two pole Sallen Key filter with a 4kHz knee. Yes I am sampling at 8kHz. The processor is pretty much idling the rest of the time so I have most of the 125uS available.

Steve