Using external xtal osc for bus clock, but keeping internal ref/FLL for BDM (ICS on S08QG)

[nimblemachines]

I'm a bit confused about the options available with the ICS on the QG. I want to do something that seems simple and obvious: run the bus clock (ICSOUT) *directly* from the external crystal oscillator, using a crystal > 5MHz (11.0952M to be exact - I want to generate 115,200 baud accurately), but *leave* the internal reference clock running and driving the FLL, so the default (~8M) BDM clock is available.

It would *seem* this is possible, since the bits that select ICSOUT (CLKS in ICSC1) and the bit that selects the internal reference source (IREFS in ICSC1) are *separate* ... but when I try to switch CLKS to the external clock, leaving IREFS set to 1, BDM goes haywire. (I can get bytes in and out, but they are garbage.)

It worries me a bit that this isn't one of the sanctioned, canonical modes of the ICS. It's *like* FBE, but the descriptions of FBE all seem to say that I have to choose the external reference as the source for the FLL - but I can't do this, since it's >5M.

I'm confused. Am I missing something?

If I had a <5M xtal on hand that I could use - one that worked nicely with 115200 - I would use it, but the only possibility is the 11.0592. I may also explore trimming the internal clock to 18.432M (bus clock of 9.216M), but I'd like to understand the ICS better.

Anyone have any experience to share?

[peg]

Hello,

Most of the modules within the QG8 use a clock source which is based on BUSCLK. Given that BUSCLK is a fixed division of two from the ICSOUT which the CPU clock is based, you don't have any option here. I draw your attention to the "System Clock Distribution Diagram" in the datasheet.

Allowing seperate clock sources would put them in different time domains. This would then need some sort of synchroniser to pass data between domains.

[nimblemachines]

But the whole point of the "alternate BDM clock" is for it to be independent of the bus clock, right? There must already be logic in the chip to synchronise between these two domains...

So I don't understand why I can't let the FLL run off the internal ref, generating _only_ the BDM (ICSLCLK) and run ICSCLK from the external reference.

- David

[peg]

Hello again David,

I missunderstood your original post. I thought you wanted to run the SCI from the FLL!

It does seem as though you should be able to do this, otherwise what is the alternate clock for? On other devices the ICS has a dedicated 8MHz oscillator just for the BDM alternate clock. The LP bit in the ICS module seems to confirm that what you are trying to do is possible. If it isn't then what is this bit for???

Finally, why do want to run the BDM on the alternate clock for anyway?

[nimblemachines]

Indeed, it *seems* that it should be possible, but I'm not sure that it is. :smileywink:

I'm using some "homegrown" tools to explore and program these chips - a Forth development system, and my own BDM implementation - initially using a 908-series part as the BDM host, since it's easy to use the built-in ROM monitor to get code onto the device, unlike with the S08.

Because my BDM is also "homegrown" it targets only the 4M and 8M BDM clocks, using routines written in software to do the bit-timing for those two speeds. I was worried that I wouldn't be able to talk to the chips unless the 8M "standard" BDM clock was also available...

It turns out not to be a problem. I was able to trim three of my S08QG's to 18.432M (9.216 bus clock) and I can still talk to them over BDM using my "8M" routines.

Cheers,

- David

[bigmac]

Hello David,

As you have not been successful in having the FLL operate (from internal reference) in FBE mode, there may well be some undocumented interlocking to inhibit this, as it does not represent a "standard" operating mode.

As an alternative, let's consider what would be required to achieve your required SCI baud rate using the standard FEI and FEE modes.

Assuming a BDIV factor of 1, the FLL output must fall within the range 16-20 MHz, giving a bus frequency range of 8-10 MHz.  There is only one bus frequency, within this range, that will accurately produce 115200 bits per second.  This is 9.216 MHz, which corresponds to a reference frequency of 36.0 kHz into the FLL.

Using FEI mode, the internal reference would need to be trimmed to 36.0 kHz.  Using FEE mode, the external crystal would need to be a power-of-2 multiple of 36.0 kHz, i.e. 36.0 kHz ... 2.304 MHz, 4.608 MHz.  Actually, a crystal frequency of 2.300 MHz or 4.600 MHz would produce a sufficiently accurate baud rate (-0.17 percent).

Regards,

Mac

[bigmac]

Hello David,

The normal requirement for FBE mode is specified as -

CLKS = 10, LP = 0, IREFS = 0

and the BDC module clock is either the bus clock, or DCOOUT divided by 2 (ICSLCLK).

With this setting, the FLL reference will be derived from the external crystal, but as you have already observed, this is not feasible for external frequencies greater than 5 MHz, consistent with the the upper limit for RDIV. To control this situation, the FLL would normal be disabled by setting LP = 1 (FBELP mode), with the loss of the ICSLCLK signal.  However, it should still be possible to use the bus clock for the BDC module.

I assume that you were attempting a setting of CLKS = 10, LP = 0, IREFS = 1, which is undocumented within the datasheet.

Regards,

Mac

[nimblemachines]

bigmac - The settings you suggest are *exactly* what I tried, and it seemed like the BDM went haywire.

I've settled on simply trimming the internal oscillator, and that works fine.

It's a bit frustrating that something obvious like this is undocumented though...

- David