S08DZ PTE1

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S08DZ PTE1

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Lundin
Senior Contributor IV

Can anyone explain to me why PTE1 is an input-only pin on the S08DZ? This makes no sense at all to me. It is shared with SCI Rx functionaity, but so is PTF, and all PTF pins can be used as I/O.

 

This is so typical for Freescale. They make a CPU with 6 ports that are -exactly- identical, except for a tiny footnote to the DDR register for PTE1 stating that it is input only. I cannot begin to express how incredibly moronic this is! No other MCU manufacturer on the market does insane, illogical things like this, but at Freescale it is tradition!

 

I remember the same thing on the HCS12Dx256 where you could map the SPI2 to different ports, but if you did, the clock and SS pins were merrily switched.

 

Unless you read the whole manual in detail while at the same time possessing photographic memory, you cannot possibly catch thing like this at design stage. As a sane engineer, you assume that sane people have routed the bond-outs. You think "ok if ports A to F work exactly the same, nobody in their right mind would change the functionality of a single pin on one of them".

 

This moronically designed little pin on the S08 now forces my company to redesign all PCBs. Just as we had to do for the moronically designed SPI2 routing on the S12 some years ago. No doubt hundreds of other companies has fallen into the same traps.

 

It is pretty obvious that some real nerd is in charge of the pin routing of Freescale MCUs, without a clue of the real world works outside of his little QFP.

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bigmac
Specialist III

Hello Lundin,

 

While your predicament is unfortunate, the block diagram for the MCU does clearly indicate that the PTE1 pin is input only, for whatever reason.  And the same block diagram appears numerous times within the reference manual (with different areas highlighted)  The footnote that you mention also appears multiple times when describing the port E registers.  I fail to see where a photographic memory would be necessary.

 

You will also consistently find that, for those MCUs where IRQ pin shares with GPIO, that pin will also be input only.  Similarly, where the BKGD/MS pin also shares with GPIO, that pin will be output only.

 

Obviously, had you been using SCI1, the problem would not have arisen.

 

Regards,

Mac

 

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Lundin
Senior Contributor IV

The block diagram has a sneaky single-ended arrow, I actually had not noticed that until now, neither had anyone else in my team. At any rate it is tiresome that you have to read Freescale manuals in a different way than you read other technical manuals. I actually believe that a lawyer would be more successful in reading them than an engineer would, as the former expects illogical fine print footnotes, while the latter expects predictable, rational science.

 

I am still mighty curious of hearing the rationale behind this. Why did PTE1 have to be an input-only, while PTF1 didn't? Or perhaps PTF1 is of the same nature, but undocumented?

 

 

"Similarly, where the BKGD/MS pin also shares with GPIO, that pin will be output only."

 

Wow that's yet another example of irrational Freescale bond out. On the S12 BKGD has to be treated as input, as it used for CPU mode selection out of reset (aka "MODC"). Failing to pull-up that pin will cause bad things to happen in the S12. But of course the pin should behave entirely differently between S12 and S08, so that engineers with experience of one family can't easily switch to the other, without first wading through all fine print foot notes!

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