S08 ADC

[KerryMac]

Greetings all,

I am implementing a single channel Analog-to-Digital read, using MC9S08LC60, but I am having inconsistent results.

Here is my setup:

* In most use the module is connected to a 12V battery, and it also uses 3V backup batteries

* A regulator drops the 12V to 3.3V 

* A diode is between the 3.3V and the backup batteries, with the feed going to the MCU's Vdd

* The Vdd while on the backups is 2.8-2.9V

* PTA0 has a line going to a point between the regulator and the diode, hence the read will be approx. 3.3V when the 12V is connected

* The current draw is 3.7mA in run

* PTA0 is initialized before the main loop:

MOV#%00010000,ADCCFG ; ADC

MOV#%00000001,APCTL1 ; Enable PTA0 as a ADC pin

* Then in a quarter second loop:

CLRADCSC1; COCO, AIEN, ADCO, ADCH (4:0)

NOP

NOP

LDAADCRL

CMP#250

BHIxxxx ; >250 = voltage from VR, 3.2V, lower V if only from internal batts

Sometimes it does not load ADCRL into A, hence a false branch occurs. Moreover, I could use this read very early in Vreset but it is even more inconsistent there.

Note that every ADC read follows a port initialization and that with a PE BDM the correct values are shown in ADCRL, $FF when the 12V source is connected and approx. one half that value when on backup batteries (2.8-2.9VDC). But it doesn't consistently load ADCRL and the failure results in $00 in A with the debugger showing $FF in ADCRL, if on 12V.

What can be done to make each read reliable?

Thanks,

KM

[KerryMac · Accepted solution]

Thanks bigmac,

Your suggestion of imbedding a ADC read in the 250 ms routine, along with reading the ADCRL value from the previous 250 ms loop, worked well. Allowing a sufficient period for consistent reads allowed me to complete this project.

ADC is new to me and I will put aside some time in the future to develop a full understanding of all of it's nuances.

Thanks again,

KM

[bigmac]

Hello KM,

From your description PTA0 would seem to be effectively connected to Vdd - is this the case?  You do not mention your connection for VrefH.  If connected to VddAD, you should get readings very close to maximum reading every time, independent of Vdd.

A better approach might be to measure the internal bandgap reference.  For a Vdd of 3.3 volt, the 8-bit reading should be in the vicinity of 93.  When Vdd drops to 2.9 volt, the reading should increase to about 106.

If the 12 volt supply is never present when running from batteries, another approach is to feed this point to PTA0, via a suitable voltage divider.

After a POR, you should wait a sufficient time for Vdd to stabilize.  This may take tens of milliseconds after POR, depending on bulk capacitors present, and other factors.

I notice that your code does not wait until COCO flag becomes set before attempting to read ADCRL.  Two NOP instructions would be insufficient to complete the conversion.  Since this part of the code executes every 250 ms, a variation would be to read the previous result, and then commence the next conversion.

LDA  ADCRL       ; Read previous resultMOV  #0,ADCSC1   ; Commence next readingCMP #xxxBHI xxxx

Regards,

Mac