Freescale support provided this answer;
Please find such decription from reference manual below.
6.4.3 SCI0 pin reassignment
After reset, SCI0 module pinouts of RxD and TxD are mapped on PTB0 and PTB1,
respectively. SOPT1[SCI0PS] bit enables to reassign SCI0 pinouts on PTA2 and PTA3
So yes, I was missing something!
Ascii