Hello @techteam, Good Day!
Thank you very much for your interest in our products.
Please consider that for the PN7161B1HN/C100 variant of the chip, the host interface is fixed to SPI during production of the device and cannot be changed. For addressing host communication issues, please make sure a correct power-up sequence of the device is taking place, please have a look at section 11.5 of the PN7160_PN7161 Data Sheet for reference on possible power-up sequences for a successful host communication.
For communicating via SPI with the chip please make sure the following pins are being handled correctly:
- HIF1 NSS (Not Target Select)
- HIF2 MOSI (Controller Out Target In)
- HIF3 MISO (Controller In Target Out)
- HIF4 SCK (Serial Clock)
And ensure the SPI communication sequence is properly met. Consider the following:
- PN7161 starts sampling when receiving a logic low at pin NSS and the clock at input pin SCK.
- SCK must be provided by the host.
- The MISO line is configured as an input in a controller device.
- The MOSI line is configured as an output in a controller device.
- MSB is sent first.
- 7 MHz maximum SPI frequency.
Please take a look at Table 15 of the same document for details on EEPROM settings to be done for SPI-bus configuration. I would recommend as well checking out section 15.2.6 for a detailed description on the SPI-bus timings that have to be considered for proper communication.
Additionally, it would be of great help if you could please share the SPI frame (by using an oscilloscope or logic analyzer) that you get when reading the MISO, MOSI, NSS and SCK pins while running the program used for communicating with the PN7161.
My best regards,
Daniel.
