Proc_FF:
pshx
psha
lda #$14
ldx #$1C
loc_1:
brclr 0 PTA *+3
sbc #0
dbnzx loc_1
rola
pula
pulx
rts
Found this code inside, maybe anyone can tell the sense of this code?
Hello,
For the MCU you are using, I assume that monitor mode uses PTA0 for serial communications. It is usual that the data rate will be 9600 baud for a bus frequency of 2.4576MHz. Now for the sub-routine:
Proc_FF: pshx
psha
lda #20
ldx #28
loc_1: ; 10 cycle loop
brclr 0,PTA,*+3 ; [5] CF = PTA0 state
sbc #0 ; [2] Subtract 0 or 1
dbnzx loc_1 ; [3] Total loop duration 280 cycles
rola ; CF set for negative value
pula
pulx
rts
It would seem that this sub-routine is part of the serial communications process. The total loop duration of 280 cycles appears to closely approximate one bit period at 9600 baud.
I guess this is used to detect a data bit state in the presence of noise. The state is tested 28 times, and needs to be high for about 70 percent of the samples for a logic high to be decoded. In this case, the ACC will have decremented to a negative value, and the ROL instruction will set the carry flag (CF).
Regards,
Mac