MC13213 SRB System Clock Configuration

[cschai]

I want to use CLKO from Modem as my clocking source to MCU for MC13213. And the frequency i need to set is 16MHz.

What i did is
a. write to modem register 0x0A with value 0x7E80 (to set the CLKO to highest frequency)
b. write to modem register 0x09 with value 0xF3EF (to enable clko_en)
c. write MCU register ICGC1 with value 0x50 (to enable external reference and choose FLL bypass and external reference mode)
d. then i wait until ERCS (bit1) on MCU register ICGS1 to be set

that we what i configure, other register i like ICGC2, i just leave it as default value after reset!

is the configuration i made correct? with that, will MCU get a 16MHz Source Clock from modem on my SRB board?

is it that, with 16MHz source clock, i will get 8M of bus frequency?

[peg]

Hi cschai,

All of what you have said makes sense, without confirming every detail the basic concept is sound.

But I have two questions:

Why do you NEED to set CLKO to 16MHz?

Why ask at all? Can't you get it too work or what?

There are hundreds of clock options available to you here. You are not restricted to FBE mode here. You could use a lower CLKO and crank it up with the FLL in FBE mode to get maximum performance if power consumption is not a problem for instance.

[cschai]

from what i read from MC1321xRM, page 4-22,it said that:

the software supporting 802.15.4 Standard application or ZigBee application often requires an MCU bus clock of 8MHz or 16 Mhz. it said that slower baud rate (SPI) may impact performance of the software in transferring data to/from the modem and lengthen the initialization time of modem.

in this SiP (System In Package), MCU and modem is communicating through SPI. And the clocking source of Modem is from a 16MHz crystal, nothing i could change this because it is in my SRB board when i buy it. Setting CLKO to 16Mhz as my MCU clocking source, so just i can meet the minimum requirement of bus clock 8Mhz.

i choose to use CLKO 16MHz (orginally from 16Mhz crystal), but not slower freq in FLL Engaged External, because I JUST FEEL (i am not sure about that) that both MCU and Modem will be using same 16Mhz crystal source without any divisor or multiplier, so when they communicate using SPI, the baud rate will be perfect matched. I JUST FEEL so...

if i suspect that with the configuration i mentioned in the question, i still cant get 16MHz of CLKO as MCU clocking source, what will be the problem? or do i miss out some important setting?

right now i didnt have any oscilloscoope to determine the CLKO. Thanks....

[rocco]

Hi, Cschai:

---

cschai wrote:
. . . I JUST FEEL (i am not sure about that) that both MCU and Modem will be using same 16Mhz crystal source without any divisor or multiplier, so when they communicate using SPI, the baud rate will be perfect matched . . .

---

You don't need to worry about baud rates with the SPI, because the SPI has it's own clock. The SPI master (the CPU, in this case) supplies a separate clock to the SPI slave (the modem) for the duration of each transfer, allowing the slave can operate on a completely asynchronous clock.

The SPI's baud-rate select bits set the SPI clock rate for a CPU that is programmed as a SPI master. But for a CPU programmed as a SPI slave, the baud-rate bits have no effect.

Hope that helps.

[cschai]

Below is what i quote at from Reference Manual, about ICG Control Register1 (ICGC1), Bit3:4-CLKS

Clock Mode Select — The CLKS bits control the clock mode. If FLL bypassed external is requested, it will not be selected until ERCS = 1. If the ICG enters Off Mode, the CLKS bits will remain unchanged. Writes to the CLKS bits will not take effect if a previous write is not complete.
The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits cannot be written to 1X until after the next reset (because the EXTAL pin was not reserved).
00 Self-clocked
01 FLL engaged, internal reference
10 FLL bypassed, external reference
11 FLL engaged, external reference
~~~~~

What does i mean by "the CLKS bits cannot be written to 1X until after the next reset"?
so if want to use FLL bypass, external reference, when can i write to this CLKS?

[peg]

Hi,

What they are saying here is that after reset you can only configure the EXTAL/XTAL pins once. The higher bit of the CLKS pair controls this and so if you change the higher bit you need to reset for it to take effect.

This should not usually be a problem if you go straight into 10 mode

I should add that this is only my interpretation of how it works, no actual confirmed experience here!

[cschai]

to reset it to take effect?
not that when we reset, all the register will back to default value?
will my the changing value back to default if i reset?

[peg]

Yeah, wasn't very clear, was I?

Reset, change, change - second change doesn't work!

Reset, change, reset, change - works! Only 1 write per reset!

[cschai]

hi peg,

ok thansk...
reset change change...