"When an interrupt occurs, The CCR value is saved on the stack before the I bit is automatically set (I would be 0 in the stacked CCR value). When the return-from-interrupt (RTI) instruction is executed to return to the main program, the act of restoring the CCR value from the stack normally clears the I bit.
When the I bit is set, the change takes effect too late in the instruction to prevent an interrupt at the instruction boundary immediately following an SEI or TAP instruction. In the case of setting I with a TAP or SEI instruction, I is actually set at the instruction boundary at the end of the TAP or SEI instruction. In the case of clearing I with a TAP or CLI instruction, I is actually cleared at the instruction boundary at the end of the TAP or SEI instruction. Because of this, the next instruction, after a CLI or TAP that cleared I, will always execute even if an interrupt was already waiting when the CLI or TAP that cleared I was executed. In the case of the RTI instruction, the CCR is restored during the first cycle of the instruction so the 1-cycle delay, associated with clearing I, expires several cycles before the RTI instruction finishes. WAIT and STOP also clear I in the middle of the instruction, so the delay expires before actually entering wait or stop mode.
"
My bad...
I'm sure there a way to get blocked though.
Even a bigger cheque for you then !?
Alvin. {RTFM}
