ICS clock trimming: how is it implemented in the Programmers

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

ICS clock trimming: how is it implemented in the Programmers

4,196 次查看
PeterK
Contributor III
Hello,
 
  I've  read the application notes on ICS clock trimming and ICG as well
  and it seems really pretty straight-forward. There was however some
  information that I missed regarding how trimming is done at the factory
  and by the the various development boards and programmers.

 At the factory: is that a trimming per individual device or some sort of average
  for the device category? What I mean do they for each chip perform a separate
    chip specific trimming? Purpose of course would be to reduce the effects of
    process variations.

Then the development boards and programmers:
    The programmers have access to precise internal clocks
    so it would seem obvious that they do this. I know it might add
   some time to the total ptogramming time, so likely an option
    But is that what they do? a device specific / per chip specific trim?


thanks a lot
  PeterK

 
标签 (1)
6 回复数

2,270 次查看
Ake
Contributor III
Hi,
When the testing of the finished MCU, a final calibration of the onboard oscillator is performed.
At room temperature the ICGTRM/ICSTRM register is changed until the frequency error is minimum.
Then this value is stored in a TRIM byte high up in the Flash EPROM.
1) Yes the trimming is individual. I think it takes a couple of ms to do it.
 
To use the TRIM value, you must read it and write it into the xysTRM register.
The manufacturers of MCU burn equipment have fixed their programs so that the TRIM value is always saved before a mass erase command is given. And later it is restored.
 
Note that if you want to have an another frequency, you can set up your own calibration value somewhere else in the Flash EPROM.
If the TRIM value is 0xff, it is replaced by the default TRM value of 0x80.
 
2)  When the MCU is later soldered on a board, with another Vdd supply, the frequnency might be slightly changed. Therefore some Flash burner manufacturers, offer an optional TRM value setting.
This is usually very simple, just click in a box in the software, and you have a fresh TRIM value.
I think it takes about 1 S to do it.
 
 
Regards,
Ake
 

2,270 次查看
peg
Senior Contributor IV
Hi Ake,



Ake wrote:

The manufacturers of MCU burn equipment have fixed their programs so that the TRIM value is always saved before a mass erase command is given. And later it is restored.
  


Hmm, which manufactures? which model? and how do you tell Codewarrior to allow this?

I though the value was always trashed and you just got the adapter to calculate a new one. Or you write it down and manually put it back in.

0 项奖励
回复

2,270 次查看
Ake
Contributor III
Hi,
P&E Micro has the CyclonePro that will automatically adjust the TRIM frequency while programming your code.
 
If you run the CodeWarrior, and have a Cyclone connected, there is a pull-down menu in the True-Time Simulator, called MultiLink/Cyclone Pro. Pull it down and select the Advanced programming/debugging.
A new window opens up. In that window is a small box that says "Calculate Trim and ....". Click it and you will get an automatic setting of the TRIM value in the Flash EPROM.
 
If you would have to handle the TRIM values by hand, it would be too cumbersome.
So I think it works really neat. But don't forget to initialize the ICG/ICSTRM register with the TRIM value when you power up.
 
Regards,
Ake
 
0 项奖励
回复

2,270 次查看
peg
Senior Contributor IV
Hello,

Yes, of course, this is how it works as I know it.
Your previous post was suggesting that you could carry the factory (or a previously calculated and burnt) trim value through an erase/reprogramme cycle.
The only way to do this is with a piece of paper. (or organic memory)

0 项奖励
回复

2,270 次查看
JimDon
Senior Contributor III
Actually, all P&E BDMs will handle trim.

0 项奖励
回复

2,270 次查看
fabio
Contributor IV
Hi,

To trim the internal reference oscillator the BDM/programmer uses a special BDC command called SYNC.

The SYNC command is fully described in the HCS08 reference manual (page 226). In short: the host drives the BKGD line low for at least 128 cycles of the slowest possible BDC clock speed.

After that, the target waits for the BKGD line to be in logic level high and drives the BKGD line for 128 BDC clock cycles. The host hardware measure this pulse, calculate the appropriate TRIM values, write then in the TRIM registers and issue a new SYNC command to measure the new BUSCLK speed.

Best regards,


0 项奖励
回复