Dear TDKamalAru,
The efficiency of the code generated depends (obviously) on the architecture of the processor. The HCS08 has very limited bit addressing instructions. If the bit field in your structure is not located in the direct page then a read-modify-write sequence of at least three instructions is required.
If you can locate your bitfield in the (very limited) direct memory space then the code will be much more efficient.
#pragma DATA_SEG __SHORT_SEG myShortSegment
S_Data DataBuffer[2];
#pragma DATA_SEG DEFAULT
DataBuffer[0].BitVars.Bits.BitVar3_rb1 = ENUM_1;
Generates the following:
0001 1402 [5] BSET 2,DataBuffer:2
This is a 2-byte instruction executing in 5 cycle.
This is compared to below when not in the direct page (4 instructions, 7 bytes, 10 cycles).
0001 450002 [3] LDHX @DataBuffer:2
0004 f6 [3] LDA ,X
0005 aa04 [2] ORA #4
0007 f7 [2] STA ,X
For comparison - If you try your code with a HCS12 chip it generates a single (4-byte,4-cycle) instruction in both case. The HCS12 has more general bit manipulation instructions.
bye
PS. Apologies - this overlaps with Bigmac's post. Composed last night but posted this morning.