HCS08QG - SPI - The SPTEF Bit And SPTIE For Transmit Interrupts

[FC]

Hello,

I have read most of the SPI discussions, but it seems the ony functional use of the SPTEF bit is for double buffered transmit operation. I know the SPTEF must be read while high before writing to the SPID to start a transfer and the SPRF being the transfer complete flag.  For an interrupt driven SPI application, what function does the SPTEF bit serve besides double buffered use?  It seems the SPI receive full interrupts need only to be enabled (assuming mode fault is not used).  I will post up my code shortly which will explain this.

Second question.  Does the SPTEF bit actually become low when the SPI transmit buffer is full? 

Lets there are back to back SPI transfers.  For the idle SPI, the SPTEF bit will set within 2 bus cycles. The second SPID write should clear the SPTEF bit since the SPI shift register contains the first byte.

Thanks

[peg]

Hello FC,

What you have posted is essentially correct.

The method I have shown in the sticky at the top of this forum is how you can totally ignore the SPTEF bit and the transmit buffer. Writes to the buffer will always fall straight through as you don't write again until the transmit buffer is empty. The SPTEF flag is only of use where you want to utilise the buffered nature of the SPI transmitter.

[bigmac]

Hello FC,

The use of buffered SPI send is of little or no value for SPI master operation.  However, for SPI slave operation, the ability to queue two bytes ready for interrogation by the master may be of some practical use.

For master operation, once the second byte is entered, there is additional (and unnecessary) risk of an overrun error occurring, especially if the clock rate is high, and other interrupts are in use.  The processing required at the completion of the first byte can be potentially delayed by the execution time of the other ISRs. There are no overrun timing issues if handling a single byte at a time (whether or not using interrupts).

Utilising interrupts for master operation is likely to be of significant value only when the SPI clock rate is very slow.  For the fast clock rates normally used, the additional time overheads associated with entering and exiting the interrupt are likely to be comparable with the byte transmission period.

Regards,

Mac