HCS08 reset when ERASE Flash

[Lodhart]

Hi,

when i try to ERASE only one sector of Flash, i get reset. I don't know why, i found a solution on this forum and google but with no solution. Interesting is that i try step the code and It will be pass. But when i just RUN the code. Reset comes.

E_FLASH_Result e_FLASH_WriteBlock(pu8 pu8_FlashPtr)/*****************************************************************************/{    /* Disable WATCHDOG */  //SOPT1_COPT = 0b00;  /* Wait for complete previous operation */  while (!FSTAT_FCCF) __RESET_WATCHDOG();                         /* DisableInterrupts */  _asm SEI;                                        /* ERASE FLASH SECTOR ------------------------------------------ */                                                                      /* Clear old error */     if (FSTAT_FACCERR == 1) FSTAT_FACCERR = 1;     /* Make sure command buffer is empty */  while(!FSTAT_FCBEF) __RESET_WATCHDOG();      *(pu8_FlashPtr) = 0xFF;  FCMD = 0x40;             /* Wait at least 4 cycles before clearing FCBEF */  _asm NOP;  _asm NOP;  _asm NOP;  _asm NOP;    /* Clear command buffer empty flag */  FSTAT_FCBEF = 1;       /* Check Access error */  if (FSTAT_FACCERR) {    FSTAT_FACCERR = 1;    return FSTAT_FACCERR;  }         /* Check Write error */  if (FSTAT_FPVIOL) {    FSTAT_FPVIOL = 1;    return FLASH_FPVIOL;  }      /* Wait for command completion or error */  do {    __RESET_WATCHDOG();  } while ((FSTAT & 0x70) == 0);          return FLASH_OK;}

 Thank you for any ideas.

[bigmac]

Hello,

Perhaps you should monitor the SRS register to ascertain the source of your unexpected resets.  If you are attempting to erase the last sector, where the interrupt vectors are located, this would be problematic.

You do not say which MCU type you are using?  The majority of 9s08 derivatives have a single flash array, so that a portion of the erase/programming code needs to be executed from RAM, as Kef has suggested.  The following function would be executed from RAM, when flash memory becomes inaccessible.  The code that preceeds, and follows the call of this function can be located within flash.

#define EXIT_MASK  FSTAT_FACCERR_MASK | FSTAT_FPVIOL_MASK | FSTAT_FCCF_MASK#define ERR_MASK   FSTAT_FACCERR_MASK | FSTAT_FPVIOL_MASK/*****************************************************************************/#pragma CODE_SEG FLASH_ROUTINES/* This function is executed from RAM, after a flash copy is transferred.   Requires 13 bytes, plus __RESET_WATCHDOG() macro size. */void flash_cmd( void){   FSTAT = FSTAT_FCBEF_MASK;           // Clear FCBEF bit - activate command   do {      __RESET_WATCHDOG();   } while ((FSTAT & EXIT_MASK) == 0); // Wait for command completion or error}#pragma CODE_SEG DEFAULT

Since the function will exit for either command completion, or for an error state, the presence of an error is easily tested using(FSTAT & ERR_MASK).  Here is an example of the flash based function that I have previoulsy used for both sector erase and single byte programming.

// Process flash commandbyte flash_proc( byte *faddr, byte data, byte fcommand){   CRITICAL();                        // Disable interrupts   FSTAT = ERR_MASK;                  // Clear FACCERR & PVIOL flags, if set   *faddr = data;                     // Write data to flash location   FCMD = fcommand;                   // Enter command   flash_cmd();                       // Execute command (from RAM)   CRITICAL_RESTORE();                // Restore previous interrupt status   return (FSTAT & ERR_MASK);         // Return FACCERR & PVIOL error status}

If you are using one of the few devices that contain two separate flash arrays, e.g. 'DZ60, the code for programming one array could be located within the other flash array, in lieu of being transferred to RAM.

Regards,

Mac

[peg]

Hello Lodhart,

It is not the fact that the SOPT register is a "write once" register and it has previously been written to, so your attempts here to disable the COP timer is in vain.

[Lodhart]

Hello Peg,

i'm sorry. The line witch SOPT1 is the last hopeless try. Of course, i know that SOPT1 is only once write register.

[kef]

1) flash is not readable (which means also that code can't run from it) while it is being erased or programmed, or while any flash command is in progress (while CCIF==0). So your flash routines must be allocated to RAM or other readable memory.

2)  if (FSTAT_FACCERR == 1) FSTAT_FACCERR = 1;  <---------- this (and other flasg manupulation code) is completely wrong.

Instead of writing one only to FACCERR bit, you write or may write ones to other FSTAT bits. Since FSTAT_FACCERR = 1 preserves contents of other than FACCERR FSTAT bits, ones are written to all bits that are set. So most likely this is an attempt to launch flash command, since most likely FCBEF bit is set. You should use this to clear FACCERR

FSTAT = FSTAT_FACCERR_MASK;