HC908QY2: PWM at 0%?

[jag]

Hello,
I have this problem:
I use the TIM module in the QY2 to create a 400Hz PWM (using CW 3.1).
Here the config:

Code:

    TSC_TSTOP = 1;    TSC_TRST  = 1;                  TSC_PS = 6;                     TMODH = 0;                     TMODL = 0x7D;                   TCH1H = 0x00;              TCH1L = 0x00;              TSC1_MS1A = 1;              TSC1_TOV1 = 1;                  TSC1_ELS1B = 1;                 TSC1_ELS1A = 0;                 TSC_TRST   = 0;                 TSC_TSTOP  = 0;                 TSC_TOIE   = 1;            

The problem is that even when TCH1 == 0 I still have a 0.8% of duty cycle on the pin (it's 20 usec long).

There is a way to have the pin low always when TCH1 == 0?

Thanks Bye Jack

[bigmac]

Hello Jack,

The problem you have encountered is because the TIM channel output becomes active when the counter reaches the TMOD value.  This means that, when the channel value is set to zero, the pulse width will actually be one TIM clock period, as you have observed.  The channel value should be set to one less than the pulse width that you require.

The way to achieve zero duty cycle is to clear the TOV bit within the TSCn register.

Note that, if you require a PWM period of 125 (0x007D), the TMOD setting will need to be 124 (0x007C).  With your present setting, the PWM period will be 126.

Regards,
Mac

[JimB]

Hi - see the section in the datasheet entitled "PWM Initialization":

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output.

I see some marginal notes in my manual imply that the "OC" time behaves differently for PWM. Also there is a query about the following phrase:

The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%.

(specifically, the suggestion that it should be $007f.)

Jim

[tonyp]

I don't know what the problem is, but as a work-around, have you tried 100% duty with negative polarity which will be the same as positive 0% duty?  Other than that you can also try direct control of the pin for 0%.

Quote from the reference manual:
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See 14.8.1 TIM Status and Control Register.