Hello Cristian,
To provide an exact baud rate of 115200, the bus frequency would need to be a multiple of 1.8432 MHz. Assuming the use of either FEI or FEE modes for generating the bus clock, the bus frequency would need to be 9.216, 16.589 or 18.432 MHz. The POR default mode is FEI.
For FEI mode, the bus frequencies 9.216 and 18.432 MHz would require a trimmed internal reference frequency of 36.0 kHz. For 16.589 MHz, the internal reference frequency would be 32.4 kHz. Either of these reference frequencies would need to be specifically calibrated with a suitable trim value. For FEE mode, the crystal frequency would need to be a power-of-2 multiple of these reference frequencies, but not exceed 5 MHz. For example, a 36.0 kHz reference would require a crystal frequency of 2.304 or 4.608 MHz. Such frequencies may not be readily available.
However, other crystal frequencies may be able to achieve sufficient accuracy for SPI operation.
Your original choice of 4.0 MHz would be problematic, i.e. 4.0 MHz would divide down to a reference frequency 31.25 kHz (the minimum allowable value). This is then multiplied by a factor of 512 for a bus frequency of 16.0 MHz (assuming BDIV factor of 1). The closest baud divisor value would be 9, which would give a baud error of -3.55 percent, very close to the usual error limit. For reliable operation, I would usually aim for an error less than 1 - 2 percent.
A crystal frequency of 4.1943 MHz (which used to be readily available ) would give a baud error of +1.14 percent.
Regards,
Mac