Clock init problems with 9S08DZ32

[BAN]

Hi!

I'm trying to start an application in 9S08DZ32 for the first time but I have serious problems when setting up the MCG. First I try the example #1 in the data sheet at page 154 (8.5.2.1) and it works fine. Then I try to change the settings just slightly by changing VDIV from 0100 ( * 16) to 0101 ( * 20) and now it won't work anymore. My target is to reach a bus frequency of 20 MHz but I first try with small increments.

Is this a valid change in VDIV or are there dependencies in other registers that I can’t understand. 

I'm using CW v6.2

[Ake]

Hi,

I believe that the highest fBUS frequency you can reach with the interal oscillator tuned at 32 kHz is 16 MHz. Do it by including

MCGC2_BDIV = 0;

(The default speed is fBUS = 8 MHz).

If you want to use the PLL part of the clock generator to get higher frequencies, you must use an external oscillator.

Regards,

Ake

[BAN]

Hi!

Yes, but the example #1 I'm referring to IS using an external clock. This example has the right prerequisites for me except for the bus frequency that should be 20 MHz. So the plan was to alter the settings in VDIV and RDIV to achieve 20 MHz but this has failed. Next try was to change the setting of VDIV only one step higher just to see what happens but it fails again just like I mentioned earlier. If VDIV is adjusted one step lower (0011) it still works. Maybe example #1 is on the 'limit' and higher bus frequencies than 8MHz can not be reached with this method???

Still confused ...