Hi Brian,
First I will presume you mean QG8,
Answer is 8MHz.
a.) Statement is WRONG!
b.) Statement is correct.
c.) Drawing is correct. The 2^n divider is controlled by BDIV which has a reset default of 01 which means /2.
Regards David
Hi Brian,
My first response is WRONG!
The sections of the manual you refer to are ALL CORRECT!
The answer is 4MHz
For an explanation refer to Figure 10.2.
Start at the internal reference clock in the middle.
It runs at nominally 16MHz.
To IREFS.
IREFS defaults to 1 which selects internal rather than external clock.
Then through programmable divider controlled by RDIV.
RDIV defaults to 000 which is divide by 1. (16MHz)
Into the FLL.
CLKS defaults to 00 which selects the output of the FLL
then to another programmable divider controlled by BDIV.
BDIV defaults to 01 which is divide by 2. (8MHz)
Now the signal is called ICSOUT.
This is then divided by 2 to produce BUSCLK.(4MHz). (as noted in OP's b) section 10.1)
Sorry if I have lead anyone astray.
Alban, quick get that note to the datasheet owner back before he thinks we are all illiterate, especially me, then you and the 53 people that read my incorrect response without comment.
Regards David
Message Edited by peg on 2006-06-08 09:39 PM