About ICG module in MC9s08AC60

[rajanjoshe]

Dear all,

I am trying to understand ICG module of above mentioned controller and i am very sorry to say the contents of datasheet is not very comprehensive ! There are certain terms in datasheet ,that are not described in details.So newcomer like me is getting problem in understanding the terms!

Anyway ,my problem is about ICG mode Section 10.5

I not at all understand terms like lock and unlock which are mentioned in relation with Internal and External! Also there is no proper explanation about "error counter" I have searched this word through out documents but didnot get its meaning ! Likewise  nunlock and nlock these are terms which are not described properly!

I really stuck on this terms so anybody  who knows please help me !

Thank you!

[BV_BV]

As for the "error counter" I think that it can be explained like that:

You got you high CPU frequency, let's say it's 16MHz.

Micro has a comparison cycle (a period) which is made by another independent internal clock. Lets' say the comparison cycle is 1ms.

So, in you comparison cycle you expect to count 16,000 CPU cycles.

This number is subctracted by let's say 15,500.  16,000-15,500 = 500

If the number goes lower than e.g. 250 or over e.g. 750 you say your CPU clock is faulty and you may want to stop your machine or send an alarm to the world.

This is what I understand from here:

FLL Lock and Loss-of-Lock Detection
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see Table 8-9 for explanation of a comparison cycle) and passes this number to
the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn. To
achieve locked status, Δn must be between nlock (min) and nlock (max). After the FLL has locked, Δn must
stay between nunlock (min) and nunlock (max) to remain locked. If Δn goes outside this range unexpectedly,
the LOLS status bit is set and remains set until cleared by software or until the MCU is reset. LOLS is
cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset
(LOLRE = 1), or by any MCU reset.

Message Edited by BV_BV on 2009-04-04 11:41 AM

[rajanjoshe]

Thank you! It was very good explanation !

[BV_BV]

I do agree the explanation of ICG in the HC08 datasheet is not really clear.

I had to go throught it more times myself.

Other microprocessor brands have an easier clock part.

Anyway, I think that your "lock" and "unlock" refers to the FLL block. 

FLL is a frequency multiplier. It multiplies the input frequency by 512.

As you know,  passing from a higher frequency to a lower one is not a problem, but passing from a lower to a  higher frequency requires a delicate circuit called the FLL (which is a brother of the PLL).

Since output frequency is not guarantee to be always stable (Vdd spikes, interferences, so on), they say the FLL is locked when it's working correctly and unlocked when the output frequency is out of control.

More, you can switch the FLL on and off, and when you switch it on, it takes some time (milliseconds ?) to be stable.

As they say:

Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or
external clock source and multiplies it to a higher frequency. Status bits provide information when
the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the
external reference clock and signals whether the clock is valid or not.

Hope it clearer.